RFR: 8366847: JFR reports incorrect number of cores on hybrid CPU

[Yasumasa Suenaga]

On hybrid CPU like Intel Arrow Lake, JFR reports incorrect number of cores in `jdk.CPUInformation`.


$ jfr print --events jdk.CPUInformation test.jfr
jdk.CPUInformation {
  startTime = 10:49:27.692 (2025-09-04)
  cpu = "Intel (null) (HT) SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 Core Intel64"
  description = "Brand: Intel(R) Core(TM) Ultra 5 225U, Vendor: GenuineIntel
Family: <unknown> (0x6), Model: <unknown> (0xb5), Stepping: 0x0
Ext. family: 0x0, Ext. model: 0xb, Type: 0x0, Signature: 0x000b0650
Features: ebx: 0x40800800, ecx: 0xfffaf38b, edx: 0xbfcbfbff
Ext. features: eax: 0x00000000, ebx: 0x00000000, ecx: 0x00000121, edx: 0x2c100800
Supports: On-Chip FPU, Virtual Mode Extensions, Debugging Extensions, Page Size Extensions, Time Stamp Counter, Model Specific Registers, Physical Address Extension, Machine Check Exceptions, CMPXCHG8B Instruction, On-Chip APIC, Fast System Call, Memory Type Range Registers, Page Global Enable, Machine Check Architecture, Conditional Mov Instruction, Page Attribute Table, 36-bit Page Size Extension, CLFLUSH Instruction, ACPI registers in MSR space, Intel Architecture MMX Technology, Fast Float Point Save and Restore, Streaming SIMD extensions, Streaming SIMD extensions 2, Self-Snoop, Hyper Threading, Thermal Monitor, Streaming SIMD Extensions 3, PCLMULQDQ, MONITOR/MWAIT instructions, Enhanced Intel SpeedStep technology, Thermal Monitor 2, Supplemental Streaming SIMD Extensions 3, Fused Multiply-Add, CMPXCHG16B, xTPR Update Control, Perfmon and Debug Capability, Process-context identifiers, Streaming SIMD extensions 4.1, Streaming SIMD extensions 4.2, x2APIC, MOVBE, Popcount instructi
 on, TSC-Deadline, AESNI, XSAVE, OSXSAVE, AVX, F16C, LAHF/SAHF instruction support, Advanced Bit Manipulations: LZCNT, SYSCALL/SYSRET, Execute Disable Bit, RDTSCP, Intel 64 Architecture, Invariant TSC"
  sockets = 1
  cores = 7
  hwThreads = 14
}


Flight record in above was created on Intel Core Ultra 5 225U. According to [datasheet](https://www.intel.com/content/www/us/en/products/sku/241861/intel-core-ultra-5-processor-225u-12m-cache-up-to-4-80-ghz/specifications.html), it has 12 cores, 14 threads. Thus JFR should report `12` in `cores`.

We tackled similar issue on [JDK-8365633](https://bugs.openjdk.org/browse/JDK-8365633), then we concluded it is difficult to calculate number of physical cores. Thus we might not set correct value at here, but we should avoid to set incorrect value at least.

This patch sets `0` to `cores` and "Hybrid Architecture" is added to `description` as following if `jdk.CPUInformation` is generated on hybrid CPU. I want to set `-1` to `cores` TBH, but I didn't because `cores` is declared as `uint` - `-1` is equivalent with `UINT_MAX`, it looks like strange at here.


jdk.CPUInformation {
  startTime = 10:48:12.420 (2025-09-04)
  cpu = "Intel (null) (HT) SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 Core Intel64"
  description = "Brand: Intel(R) Core(TM) Ultra 5 225U, Vendor: GenuineIntel
Family: <unknown> (0x6), Model: <unknown> (0xb5), Stepping: 0x0
Ext. family: 0x0, Ext. model: 0xb, Type: 0x0, Signature: 0x000b0650
Features: ebx: 0x42800800, ecx: 0xfffaf38b, edx: 0xbfcbfbff
Ext. features: eax: 0x00000000, ebx: 0x00000000, ecx: 0x00000121, edx: 0x2c100800
Supports: On-Chip FPU, Virtual Mode Extensions, Debugging Extensions, Page Size Extensions, Time Stamp Counter, Model Specific Registers, Physical Address Extension, Machine Check Exceptions, CMPXCHG8B Instruction, On-Chip APIC, Fast System Call, Memory Type Range Registers, Page Global Enable, Machine Check Architecture, Conditional Mov Instruction, Page Attribute Table, 36-bit Page Size Extension, CLFLUSH Instruction, ACPI registers in MSR space, Intel Architecture MMX Technology, Fast Float Point Save and Restore, Streaming SIMD extensions, Streaming SIMD extensions 2, Self-Snoop, Hyper Threading, Thermal Monitor, Streaming SIMD Extensions 3, PCLMULQDQ, MONITOR/MWAIT instructions, Enhanced Intel SpeedStep technology, Thermal Monitor 2, Supplemental Streaming SIMD Extensions 3, Fused Multiply-Add, CMPXCHG16B, xTPR Update Control, Perfmon and Debug Capability, Process-context identifiers, Streaming SIMD extensions 4.1, Streaming SIMD extensions 4.2, x2APIC, MOVBE, Popcount instructi
 on, TSC-Deadline, AESNI, XSAVE, OSXSAVE, AVX, F16C, LAHF/SAHF instruction support, Advanced Bit Manipulations: LZCNT, SYSCALL/SYSRET, Execute Disable Bit, RDTSCP, Intel 64 Architecture, Invariant TSC, Hybrid Architecture"
  sockets = 1
  cores = 0
  hwThreads = 14
}


This change affects showing information only, would not change the behavior like active processor count.

-------------

Commit messages:
 - Revert "Update condition"
 - Update condition
 - Add fallback code if logical_cpus == 0
 - 8365633: JFR reports incorrect number of cores on hybrid CPU

Changes: https://git.openjdk.org/jdk/pull/27080/files
  Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=27080&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8366847
  Stats: 13 lines in 1 file changed: 10 ins; 0 del; 3 mod
  Patch: https://git.openjdk.org/jdk/pull/27080.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/27080/head:pull/27080

PR: https://git.openjdk.org/jdk/pull/27080