RFR: 8359378: aarch64: crash when using -XX:+UseFPUForSpilling

[Boris Ulasevich]

AArch64 BarrierSetAssembler path assumes only FP/vector ideal regs reach the FP spill/restore encoding. With -XX:+UseFPUForSpilling Register Allocator may allocate scalar values in FP registers. When such values (Op_RegI/Op_RegN/Op_RegL/Op_RegP) hit `BarrierSetAssembler::encode_float_vector_register_size`, we trip ShouldNotReachHere in release build and **"unexpected ideal register"** assertion in debug build.

Fix: teach the encoder to handle scalar ideal regs when they physically live in FP regs:
- treat Op_RegI / Op_RegN as 32-bit (single slot) - same class as Op_RegF
- treat Op_RegL / Op_RegP as 64-bit (two slots) - same class as Op_RegD

Related:
- reproduced since #19746
- spilling logic: 
  - #18967
  - #17977

Testing: tier1-3 with javaoptions -Xcomp -Xbatch -XX:+UseFPUForSpilling on AARCH

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Commit messages:
 - 8359378: arch64: crash when using -XX:+UseFPUForSpilling

Changes: https://git.openjdk.org/jdk/pull/27350/files
  Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=27350&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8359378
  Stats: 5 lines in 1 file changed: 4 ins; 0 del; 1 mod
  Patch: https://git.openjdk.org/jdk/pull/27350.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/27350/head:pull/27350

PR: https://git.openjdk.org/jdk/pull/27350