RFR: 8365147: AArch64: Replace DMB + LD + DMB with LDAR for C1 volatile field loads [v2]

[Andrew Haley]

On Thu, 18 Sep 2025 07:50:33 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> Also have just finished running jcstress and it seems to pass fine.
>
> @spchee , are you still working on this?

> Hi @theRealAph, Thank you for checking. @spchee is currently unavailable. I will be taking over this work.
> 
> Following the [#26748 (comment)](https://github.com/openjdk/jdk/pull/26748#discussion_r2287427842) discussion, would it be possible to confirm whether there is a current use-case for `AlwaysAtomicAccesses`?

There is, but the C1 implementation for `AlwaysAtomicAccesses` has a bug. (Or it has an unfortunate feature; your mileage may vary.) The current way that `AlwaysAtomicAccesses` works is to mark all accesses as effectively volatile, but this is unnecessary on AArch64 because all naturally-aligned accesses are single-copy atomic. Therefore, the logic here


void BarrierSetC1::store_at_resolved(LIRAccess& access, LIR_Opr value) {
  DecoratorSet decorators = access.decorators();
  bool is_volatile = (decorators & MO_SEQ_CST) != 0;
  bool is_atomic = is_volatile || AlwaysAtomicAccesses;


could be fixed by something like

`  bool is_atomic = is_volatile || (AlwaysAtomicAccesses & ! CPU_IS_SINGLE_COPY_ATOMIC);
`

But that could be handled in another patch.

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PR Comment: https://git.openjdk.org/jdk/pull/26748#issuecomment-3311483034