RFR: 8367611: Enable vblendvp[sd] on Future ECore [v3]

[Jatin Bhateja]

On Tue, 23 Sep 2025 19:08:53 GMT, Mohamed Issa <missa at openjdk.org> wrote:

> > Hi @missa-prime , VBLENDVPS was always supported by AVX2 targets. We enabled its software emulation for performance reasons, as these needs microcode assistance on AVX2 targets.
> > <img alt="image" width="1187" height="228" src="https://private-user-images.githubusercontent.com/59989778/492717717-a32c66bb-df82-4534-925a-1c75dd78bea7.png?jwt=eyJ0eXAiOiJKV1QiLCJhbGciOiJIUzI1NiJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3NTg2MTk2NjcsIm5iZiI6MTc1ODYxOTM2NywicGF0aCI6Ii81OTk4OTc3OC80OTI3MTc3MTctYTMyYzY2YmItZGY4Mi00NTM0LTkyNWEtMWM3NWRkNzhiZWE3LnBuZz9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNTA5MjMlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjUwOTIzVDA5MjI0N1omWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPTg5ZTI3N2EyMjAyNDE0ZTBiMGM0ODI0ZTM4NjcwMmFiNDVhNDlkYmViNjhiMTVmOTRmZWY2MmFmZmMwMjIyZGQmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0In0.aiPMZsYuQMVbnY0DLqkoycN0SxmckTMUbdGckxNxdoQ">
> > It seems your PR is lifting this limitation for Darkmont under a constraint on dst and src1 register equivalence?
> > Please add appropriate comments in code and documentary reference to the relevant section of the Intel Architectural Set Extension Manual.
> 
> Currently, there is no public documentation mentioning the (dst == src1) register optimization on Darkmont. Once it's available, I'll add comments and reference it.

Thanks @missa-prime , this is another use case apart from NDD demotion where [register biasing](https://github.com/openjdk/jdk/pull/26283) may be useful to trigger this micro-architectural optimization.

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PR Comment: https://git.openjdk.org/jdk/pull/27354#issuecomment-3326322929