RFR: 8368366: RISC-V: AlignVector is mistakenly set to AvoidUnalignedAccesses

[Fei Yang]

On Tue, 23 Sep 2025 07:21:47 GMT, Fei Yang <fyang at openjdk.org> wrote:

> Hi, please consider this small change fixing setting of `AlignVector` flag on RISC-V.
> 
> According to the latest RISC-V linux hardware probing syscall [1], the performance of misaligned memory accesses
> has been divided into two cases: `RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF` and `RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`
> for scalar and vector respectively. And `RISCV_HWPROBE_KEY_CPUPERF_0` is now deprecated and it returns similar values
> to `RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`.
> 
> Previously, we use `RISCV_HWPROBE_KEY_CPUPERF_0` to detect support for misaligned memory accesses and reflect the result
> on these VM flags: `AvoidUnalignedAccesses`, `UseUnalignedAccesses` and `AlignVector`. But it doesn't seem correct to update
> `AlignVector` according to this value. And this is causing issues on RISC-V hardwares which have fast misaligned accesses only
> for the scalar case. I witnessed SIGBUG error on these hardwares when doing vector misaligned accesses.
> 
> So we should align AlignVector with `RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF` instead. This patch just reverts the previous
> setting of AlignVector and just let it have the default value which is true. I will try to add detection in a separate PR
> for `RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF` and update `AlignVector` accordingly.
> 
> [1] https://docs.kernel.org/arch/riscv/hwprobe.html

Thanks all for the reviews.

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PR Comment: https://git.openjdk.org/jdk/pull/27445#issuecomment-3327956706