RFR: 8367692: RISC-V: Align post call nop [v2]

[Fei Yang]

On Thu, 25 Sep 2025 07:36:22 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 359:
>> 
>>> 357: void MacroAssembler::post_call_nop() {
>>> 358:   assert(!in_compressible_scope(), "Must be");
>>> 359:   assert_alignment(pc());
>> 
>> Does the first assertion make sense here? Seems to me the second one will just suffice.
>
> The code today to avoid C-instructions by:
> - We do not have nop -> c.nop conversion.
> - We use zr as destination
> 
> Instead of relying of this 'trickery', I'm saying these instructions are not compressed and user have to turn them off before calling here.
> I.e. now this code will work with nop->c.nop conversion and using another register in the li32. (which is very sneaky way to get 4 byte instructions)

Mind you that the `nop()` and `li32(zr, 0)` are the `callback` for the relocate. And this callback is invoked under a IncompressibleScope [1].

[1] https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/riscv/assembler_riscv.hpp#L2851

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PR Review Comment: https://git.openjdk.org/jdk/pull/27467#discussion_r2378446658