RFR: 8368722: Several vector load/store tests fail on riscv without support for misaligned vector access

[Dingli Zhang]

Hi,
Can you help to review this patch? Thanks!

In `*VectorLoadStoreTests.java`,  `loadMemorySegmentMaskIOOBE` and `storeMemorySegmentMaskIOOBE` may fail because `int index = fi.apply((int) a.byteSize())` can generate random indices that result in misaligned addresses, leading to SIGBUS on hardware that disallows misaligned vector accesses.

Some RISC-V hardware supports fast misaligned scalar accesses but not vector ones, which causes SIGBUS when executing these tests with misaligned vector memory operations.

So we should adjusted index to align with the element byte size in these tests.

### Test (fastdebug)
- [x] Run jdk_vector on k1
- [x] Run jdk_vector on x86_64 and ARM64

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Commit messages:
 - 8368722: RISC-V: Several vector load/store tests fail on riscv without support for misaligned vector access

Changes: https://git.openjdk.org/jdk/pull/27506/files
  Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=27506&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8368722
  Stats: 62 lines in 31 files changed: 0 ins; 0 del; 62 mod
  Patch: https://git.openjdk.org/jdk/pull/27506.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/27506/head:pull/27506

PR: https://git.openjdk.org/jdk/pull/27506