RFR: 8367692: RISC-V: Align post call nop [v5]

[Hamlin Li]

On Thu, 25 Sep 2025 12:44:01 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> Hi please, consider.
>> 
>> As ziccif require instructions to natural aligned to be atomic the 4 byte post call nop must be aligned.
>> But I don't want to add a c.nop(2b) to align the nop(4b) which means the jal(r) must also be algined.
>> As we have no utility to aligned the end of an instruction sequence the call it self is aligned and uses only 4 byte instructions. Only in the case where we could use an two c-instruction we may loose space.
>> 
>> Thanks, Robbin
>
> Robbin Ehn has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Use relocation spec as marker.

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 358:

> 356: 
> 357: void MacroAssembler::post_call_nop() {
> 358:   assert(!in_compressible_scope(), "Must be");

Maybe `do_compress` is better? All other places use `do_compress`.
Similar suggestion as below.

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PR Review Comment: https://git.openjdk.org/jdk/pull/27467#discussion_r2382034698