RFR: 8368722: RISC-V: Several vector load/store tests fail on riscv without support for misaligned vector access

[Vladimir Ivanov]

On Fri, 26 Sep 2025 01:44:19 GMT, Dingli Zhang <dzhang at openjdk.org> wrote:

> Hi,
> Can you help to review this patch? Thanks!
> 
> In `*VectorLoadStoreTests.java`,  `loadMemorySegmentMaskIOOBE` and `storeMemorySegmentMaskIOOBE` may fail because `int index = fi.apply((int) a.byteSize())` can generate random indices that result in misaligned addresses, leading to SIGBUS on hardware that disallows misaligned vector accesses.
> 
> Some RISC-V hardware supports fast misaligned scalar accesses but not vector ones, which causes SIGBUS when executing these tests with misaligned vector memory operations.
> 
> So we should adjusted index to align with the element byte size in these tests.
> 
> ### Test
> - [x] Run jdk_vector on k1
> - [x] Run jdk_vector on x86_64 and ARM64

That's a good point. I didn't realize it at first, but there's no point in enabling VM support when misaligned vector memory operations aren't natively supported by the JVM. C2 relies on `LoadVector`/`StoreVector` support for any vector operation (when performing vector boxing/unboxing for arguments & result). If those operations aren't supported, there's no way to intrinsify any other vector operations. 

So, either you introduce an emulation for `LoadVector`/`StoreVector` when misaligned vector accesses aren't supported or completely disable VM support by setting `-XX:-EnableVectorSupport`.

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PR Comment: https://git.openjdk.org/jdk/pull/27506#issuecomment-3347871216