RFR: JDK-8214527 AArch64: ZGC for Aarch64

[Andrew Dinn]

On 13/06/2019 11:13, Stuart Monteith wrote:
> I also thought that the comment should be "64-bit" rather than
> "128-bit", but what I did was consistent with v0_reg to v3_reg. I
> presume one of them is wrong.
Yes, Ningsheng is correct. The x86 equivalents for AArch64 registers V0,
V0_H, V0_J and V0_K etc are declared with names XMM0, XMM0b, XMM0c and
XMM0d etc. The 64 bit vector (VecD) registers are allocated as pairs
like {XMM0, XMM0b} etc. So, the equivalent AArch64 pairs {V0, V0_H} etc
also correspond to VecD registers. So, the original comment ought to be
corrected to say 64 bits.

Also, it was probably a misnomer to use _H/_J/_K suffices for the
AArch64 names. I believe the _H suffix on an general purpose register
was meant to identify the high half of a 64 bit register. The b/c/d
suffices on xmm float registers identify successive higher 32 bit
elements of the float register. We probably should have followed the
same convention with AArch64 i.e. V0b, V0c V0d but it is not a big
problem that we have not.

Another thing: those 4 original register class definitions (v0_reg etc)
are currently being used to define fixed target tmp register operands
(vRegD_V0, etc) for specific instruct definitions (string_compare,
string_inflate etc). It would be better if the allocator was allowed to
pick registers rather than forcing the instructions to use these
specific targets. Still, that is probably best left for a follow-up patch.

regards,


Andrew Dinn
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