RFR(S): 8229422: Taskqueue: Outdated selection of weak memory model platforms

[Andrew Haley]

On 1/14/20 3:52 PM, Doerr, Martin wrote:

> good catch. I think you're right. A multi-copy-atomic, but weak
> architecture (e.g. aarch64) needs an instruction which orders both
> volatile loads.

Good, I thought so.

Given that TSO machines define OrderAccess::acquire() as no more than
a compiler barrier, I believe that we could do something like

#ifdef CPU_MULTI_COPY_ATOMIC
   OrderAccess::acquire();
#else
   OrderAccess::fence();
#endif

-- 
Andrew Haley  (he/him)
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
https://keybase.io/andrewhaley
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