RFR: 8366847: JFR reports incorrect number of cores on hybrid CPU [v2]

[Erik Gahlin]

On Tue, 9 Sep 2025 08:29:09 GMT, Yasumasa Suenaga <ysuenaga at openjdk.org> wrote:

>> On hybrid CPU like Intel Arrow Lake, JFR reports incorrect number of cores in `jdk.CPUInformation`.
>> 
>> 
>> $ jfr print --events jdk.CPUInformation test.jfr
>> jdk.CPUInformation {
>>   startTime = 10:49:27.692 (2025-09-04)
>>   cpu = "Intel (null) (HT) SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 Core Intel64"
>>   description = "Brand: Intel(R) Core(TM) Ultra 5 225U, Vendor: GenuineIntel
>> Family: <unknown> (0x6), Model: <unknown> (0xb5), Stepping: 0x0
>> Ext. family: 0x0, Ext. model: 0xb, Type: 0x0, Signature: 0x000b0650
>> Features: ebx: 0x40800800, ecx: 0xfffaf38b, edx: 0xbfcbfbff
>> Ext. features: eax: 0x00000000, ebx: 0x00000000, ecx: 0x00000121, edx: 0x2c100800
>> Supports: On-Chip FPU, Virtual Mode Extensions, Debugging Extensions, Page Size Extensions, Time Stamp Counter, Model Specific Registers, Physical Address Extension, Machine Check Exceptions, CMPXCHG8B Instruction, On-Chip APIC, Fast System Call, Memory Type Range Registers, Page Global Enable, Machine Check Architecture, Conditional Mov Instruction, Page Attribute Table, 36-bit Page Size Extension, CLFLUSH Instruction, ACPI registers in MSR space, Intel Architecture MMX Technology, Fast Float Point Save and Restore, Streaming SIMD extensions, Streaming SIMD extensions 2, Self-Snoop, Hyper Threading, Thermal Monitor, Streaming SIMD Extensions 3, PCLMULQDQ, MONITOR/MWAIT instructions, Enhanced Intel SpeedStep technology, Thermal Monitor 2, Supplemental Streaming SIMD Extensions 3, Fused Multiply-Add, CMPXCHG16B, xTPR Update Control, Perfmon and Debug Capability, Process-context identifiers, Streaming SIMD extensions 4.1, Streaming SIMD extensions 4.2, x2APIC, MOVBE, Popcount instru
 ction, TSC-Deadline, AESNI, XSAVE, OSXSAVE, AVX, F16C, LAHF/SAHF instruction support, Advanced Bit Manipulations: LZCNT, SYSCALL/SYSRET, Execute Disable Bit, RDTSCP, Intel 64 Architecture, Invariant TSC"
>>   sockets = 1
>>   cores = 7
>>   hwThreads = 14
>> }
>> 
>> 
>> Flight record in above was created on Intel Core Ultra 5 225U. According to [datasheet](https://www.intel.com/content/www/us/en/products/sku/241861/intel-core-ultra-5-processor-225u-12m-cache-up-to-4-80-ghz/specifications.html), it has 12 cores, 14 threads. Thus JFR should report `12` in `cores`.
>> 
>> We tackled similar issue on [JDK-8365633](https://bugs.openjdk.org/browse/JDK-8365633), then we concluded it is difficult to calculate number of physical cores. Thus we might not set correct value at here, but we should avoid to set incorrect value at least.
>> 
>> This patc...
>
> Yasumasa Suenaga has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Use jmc_undefined_long if runs on hybrid CPU

It should not be a problem to change to type long. Values are stored as compressed integers, but you might want to check the event in JMC just to be sure. Problem might be the API, e.g. int cores = event.getInt("cores") or Integer cores = event.getValue("cores").

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PR Comment: https://git.openjdk.org/jdk/pull/27080#issuecomment-3270024207