RFR(M): 8155949: Support relaxed semantics in cmpxchg

[Hiroshi H Horii]

Hi All,

Can I please request reviews for the following change?

Code change:
http://cr.openjdk.java.net/~mdoerr/8155949_relaxed_cas/webrev.01/

This change follows the discussion started from these mails.
http://mail.openjdk.java.net/pipermail/hotspot-runtime-dev/2016-April/018960.html
http://mail.openjdk.java.net/pipermail/hotspot-runtime-dev/2016-April/019148.html
http://mail.openjdk.java.net/pipermail/hotspot-runtime-dev/2016-May/019320.html

Description:
This change provides relaxed compare-and-exchange by introducing
relaxed memory order. As described in atomic_linux_ppc.inline.hpp, 
the current implementation of cmpxchg is fence_cmpxchg_acquire. 
This implementation is useful for general purposes because twice calls of 
sync before and after cmpxchg will provide strict consistency. 
However, they sometimes cause overheads because sync instructions are 
very expensive in the current POWER chip design.

We confirmed this change improves performance of copy_to_survivor
in the parallel GC. However, we will need more investigation of GC 
by more experts. So, We would like to request a review of the change
of cmpxchg first (as Martin requested).
http://mail.openjdk.java.net/pipermail/hotspot-runtime-dev/2016-April/019188.html

Summary of source code changes:

* src/share/vm/runtime/atomic.hpp 
     - Defines enum memory_order and adds a parameter to cmpxchg.

* src/share/vm/runtime/atomic.cpp
* src/os_cpu/bsd_x86/vm/atomic_bsd_x86.inline.hpp
* src/os_cpu/bsd_zero/vm/atomic_bsd_zero.inline.hpp
* src/os_cpu/linux_aarch64/vm/atomic_linux_aarch64.inline.hpp
* src/os_cpu/linux_sparc/vm/atomic_linux_sparc.inline.hpp
* src/os_cpu/linux_x86/vm/atomic_linux_x86.inline.hpp
* src/os_cpu/linux_zero/vm/atomic_linux_zero.inline.hpp
* src/os_cpu/solaris_sparc/vm/atomic_solaris_sparc.inline.hpp
* src/os_cpu/solaris_x86/vm/atomic_solaris_x86.inline.hpp
* src/os_cpu/windows_x86/vm/atomic_windows_x86.inline.hpp
     - Added a parameter for each cmpxchg function to follow
        the change of atomic.hpp. Their implementations are not changed.

* src/os_cpu/aix_ppc/vm/atomic_aix_ppc.inline.hpp
* src/os_cpu/linux_ppc/vm/atomic_linux_ppc.inline.hpp
     - Added a parameter for each cmpxchg function to follow
        the change of atomic.hpp. In addition, implementations 
        are changed corresponding to the specified memory_order.

Regards,
Hiroshi
-----------------------
Hiroshi Horii, Ph.D.
IBM Research - Tokyo