RFR: 8253843: AArch64: Use ishst for storestore barrier

[Andrew Haley]

On 30/09/2020 17:29, Alan Hayward wrote:
> AArch64 orderAccess uses gcc built in atomic functions, which expand
> inline to DMB barrier instructions.  Specifically, they call the following:
>
> FULL_MEM_BARRIER -> DMB ISH
> READ_MEM_BARRIER -> DMB ISHLD
> WRITE_MEM_BARRIER -> DMB ISH
>
> However, storestore should be optimised to use ISHST.
>
> In addition, __sync_synchronize is marked as legacy. See:
> https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html
>
> In order for the code to match,

To match what?

> I switched everything to call dmbs directly.

We are now able to use modern C++, which means that we can use real
C++ atomic operations. Going back to inline asms would be a
regression.

The trouble with using asms for this is that the compiler does not
know what is going on inside an asm. If you use an asm with a memory
clobber for a StoreStore barrier, the compiler has to treat the asm as
a full memory barrier, so it cannot move any loads and stores across
the StoreStore. So, paradoxically, you might be making things worse.

> Also, add AArch64 to the orderAccess documentation table.

Please don't. it's more complicated than that, and it's not necessary.

-- 
Andrew Haley  (he/him)
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
https://keybase.io/andrewhaley
EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671