RFR: 8288904: Incorrect memory ordering in UL [v2]

[Patricio Chilano Mateo]

On Wed, 22 Jun 2022 21:28:12 GMT, Johan Sjölén <duke at openjdk.org> wrote:

>> Right but isn't there a control dependency that the hardware will still obey? Or can the hardware write to memory even if that path is never taken?
>> Regarding UB, I could paste the assembly of that instead (maybe I should have done that). My question was whether the cpu can execute that write instruction before even knowing if that branch will be taken.
>> Note: I found this interesting article about control dependencies (https://urldefense.com/v3/__https://lwn.net/Articles/860037/__;!!ACWV5N9M2RV99hQ!Kzs6Cjo0qIr6Enxz-LcQe8CTnxEOq_LZ2yjWnN-gBsKOmvftMw3Mz2vw26DykXzXasWmnKpJbKlQJ8njG3Fv-jAHAojE4pM_qWEc$ ). It mentions that the hardware will respect that dependency but there could be some aggressive compiler optimizations on some cases. I don't think that applies here though.
>> @fisk sorry, not sure I understood the example.
>
> @pchilano, it seems that it is true that a control dependency establishes that writes are not moved above the read of a control branch (as we do not know which, if any, branch is taken before the read is done). read-on-read allows for moving it up however.
> 
> For example:
> 
> 
> // OK
> x = true;
> while(x == true) { }
> y = a[0];
> ~>
> x = true;
> y = a[0];
> while(x == true) {}
> // NOT OK
> x = true;
> while(x == true) { }
> a[0] = 5;
> ~>
> x = true;
> a[0] = 5;
> while(x == true) {}
> 
> 
> Source:
> 
> https://urldefense.com/v3/__https://www.cl.cam.ac.uk/*pes20/ppc-supplemental/test7.pdf__;fg!!ACWV5N9M2RV99hQ!Kzs6Cjo0qIr6Enxz-LcQe8CTnxEOq_LZ2yjWnN-gBsKOmvftMw3Mz2vw26DykXzXasWmnKpJbKlQJ8njG3Fv-jAHAojE4pQsVJOK$  section 4.2 and 4.4
> 
> I believe that that means that this barrier is unnecessary, but it's good manners to do the `Atomic::load`.
> 
> Nice catch :-).

@jdksjolen, @fisk thanks for the investigation and linked documents! Mmm there seems to be contradictory definitions then. I also found [1] which as I understand it defines there should be an order between those instructions (sections B2.3.2 and B2.3.3; there is even an intent Note about that). But the fact that we have to look this up and check the fine print is already surprising for me. I thought any cpu would provide that guarantee.
 
[1] Arm Architecture Reference Manual: https://urldefense.com/v3/__https://documentation-service.arm.com/static/623b2de33b9f553dde8fd3b0__;!!ACWV5N9M2RV99hQ!Kzs6Cjo0qIr6Enxz-LcQe8CTnxEOq_LZ2yjWnN-gBsKOmvftMw3Mz2vw26DykXzXasWmnKpJbKlQJ8njG3Fv-jAHAojE4m07XJSL$ 

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PR: https://git.openjdk.org/jdk/pull/9225