Seeing error in one test on ARM: org.openjdk.jcstress.tests.volatiles.ReadTwiceOverVolatileReadTest

[White, Derek]

Hi Aleksey,


I want to nail down the nearly obvious, because the next level get tricky to me real fast.

The result (1, 0, 0) n this test means that actor2() read and stored x as 1, read and stored y as 0 (so far, so good), and read and stored X as 0. Is this correct?

Thanks,

 -Derek


-----Original Message-----
From: Aleksey Shipilev [mailto:shade at redhat.com] 
Sent: Thursday, February 23, 2017 5:19 AM
To: White, Derek <Derek.White at cavium.com>; jcstress-dev at openjdk.java.net
Subject: Re: Seeing error in one test on ARM: org.openjdk.jcstress.tests.volatiles.ReadTwiceOverVolatileReadTest

Hi Derek,

On 02/22/2017 11:49 PM, White, Derek wrote:
> Could this be a test bug? Thanks!

>From the JMM standpoint, this is a test bug. JMM allows (1, 0, 0) there. It is also obvious we have a missing outcome, because there are 8 cases to cover, and we only have 7.

Fixed:
 http://hg.openjdk.java.net/code-tools/jcstress/rev/f4757f44c8b6

What I find alarming though, is that generated code has reads in actor2() in order. Having a rare case when you see non-coherent read of $x must mean one of two things: a) there is an intermediate OSR stub that got compiled a little differently -- and this is fine; b) your host machine is not always coherent -- and this is *not* fine for ARM.

Coherency failures should have been caught by Opaque tests, like JMMSample_03:
 http://hg.openjdk.java.net/code-tools/jcstress/file/f4757f44c8b6/jcstress-samples/src/main/java/org/openjdk/jcstress/samples/JMMSample_03_Coherence.java

Thanks,
-Aleksey

> public class ReadTwiceOverVolatileReadTest {
>     int x;
>     volatile int y;
> 
>     @Actor
>     public void actor1() {
>         x = 1;
>         y = 1;
>     }
>     @Actor
>     public void actor2(IntResult3 r) {
>         r.r1 = x;
>         r.r2 = y;
>         r.r3 = x;
>     }
> }

...

> === actor2() ===
> --- C1 ---:
>   0x0000ffff6c9ad068: ldr     w11, [x1,#12]   ;*getfield x {reexecute=0 rethrow=0 return_oop=0}
>                                                 ; - (line 63)
>   0x0000ffff6c9ad06c: cbz     x2, 0x0000ffff6c9ad09c
>                                                 ;*putfield r1 {reexecute=0 rethrow=0 return_oop=0}
>                                                 ; - (line 63)
>   0x0000ffff6c9ad070: add     x10, x1, #0x10
>   0x0000ffff6c9ad074: ldar    w10, [x10]
>   0x0000ffff6c9ad078: str     w11, [x2,#12]   ;*getfield y {reexecute=0 rethrow=0 return_oop=0}
>                                                 ; - (line 64)
>   0x0000ffff6c9ad07c: ldr     w12, [x1,#12]
>   0x0000ffff6c9ad080: str     w12, [x2,#20]   ;*putfield r3 {reexecute=0 rethrow=0 return_oop=0}
>                                                 ; - (line 65)
> 
>   0x0000ffff6c9ad084: str     w10, [x2,#16]   ;*getfield x {reexecute=0 rethrow=0 return_oop=0}
>                                                 ; - (line 63)
> --- C2 ---:
>   0x0000ffff87d8923c: ldr     w0, [x1,#12]    ;*getfield x {reexecute=0 rethrow=0 return_oop=0}
>                                                 ; - (line 63)
>   0x0000ffff87d89240: str     w0, [x2,#12]    ;*putfield r1 {reexecute=0 rethrow=0 return_oop=0}
>                                                 ; - (line 63)
>                                                 ; implicit exception:
>   0x0000ffff87d89244: ldr     w0, [x1,#16]
>   0x0000ffff87d89248: dmb     ishld           ;*getfield y {reexecute=0 rethrow=0 return_oop=0}
>                                                 ; - (line 64)
>   0x0000ffff87d8924c: str     w0, [x2,#16]    ;*putfield r2 {reexecute=0 rethrow=0 return_oop=0}
>                                                 ; - (line 64)
>   0x0000ffff87d89250: ldr     w0, [x1,#12]    ;*getfield x {reexecute=0 rethrow=0 return_oop=0}
>                                                 ; - (line 65)
>   0x0000ffff87d89254: str     w0, [x2,#20]    ;*putfield r3 {reexecute=0 rethrow=0 return_oop=0}
>