git: openjdk/jdk: 8295703: RISC-V: Remove implicit noreg temp register arguments in MacroAssembler

[Fei Yang]

Changeset: ef62b614
Author:    Fei Yang <fyang at openjdk.org>
Date:      2022-10-21 02:29:45 +0000
URL:       https://git.openjdk.org/jdk/commit/ef62b614d1760d198dcb7f5f0794fc3dc55587a7

8295703: RISC-V: Remove implicit noreg temp register arguments in MacroAssembler

Reviewed-by: shade, fjiang

! src/hotspot/cpu/riscv/interp_masm_riscv.cpp
! src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
! src/hotspot/cpu/riscv/methodHandles_riscv.cpp