git: openjdk/jdk: 8293290: RISC-V: Explicitly pass a third temp register to MacroAssembler::store_heap_oop

[Fei Yang]

Changeset: 5bed9f76
Author:    Fei Yang <fyang at openjdk.org>
Date:      2022-09-05 10:02:08 +0000
URL:       https://git.openjdk.org/jdk/commit/5bed9f767507bb0f123247d149ead84d2d635f52

8293290: RISC-V: Explicitly pass a third temp register to MacroAssembler::store_heap_oop

Reviewed-by: shade

! src/hotspot/cpu/riscv/gc/g1/g1BarrierSetAssembler_riscv.cpp
! src/hotspot/cpu/riscv/gc/g1/g1BarrierSetAssembler_riscv.hpp
! src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp
! src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.hpp
! src/hotspot/cpu/riscv/gc/shared/cardTableBarrierSetAssembler_riscv.cpp
! src/hotspot/cpu/riscv/gc/shared/cardTableBarrierSetAssembler_riscv.hpp
! src/hotspot/cpu/riscv/gc/shared/modRefBarrierSetAssembler_riscv.cpp
! src/hotspot/cpu/riscv/gc/shared/modRefBarrierSetAssembler_riscv.hpp
! src/hotspot/cpu/riscv/gc/shenandoah/shenandoahBarrierSetAssembler_riscv.cpp
! src/hotspot/cpu/riscv/gc/shenandoah/shenandoahBarrierSetAssembler_riscv.hpp
! src/hotspot/cpu/riscv/gc/z/zBarrierSetAssembler_riscv.cpp
! src/hotspot/cpu/riscv/gc/z/zBarrierSetAssembler_riscv.hpp
! src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
! src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
! src/hotspot/cpu/riscv/stubGenerator_riscv.cpp
! src/hotspot/cpu/riscv/templateTable_riscv.cpp