git: openjdk/jdk: 8293769: RISC-V: Add a second temporary register for BarrierSetAssembler::load_at

[Fei Yang]

Changeset: 7376c552
Author:    Fei Yang <fyang at openjdk.org>
Date:      2022-09-14 23:50:35 +0000
URL:       https://git.openjdk.org/jdk/commit/7376c55219ce2107afb9197e2452e7122d86ef52

8293769: RISC-V: Add a second temporary register for BarrierSetAssembler::load_at

Reviewed-by: fjiang, shade

! src/hotspot/cpu/riscv/gc/g1/g1BarrierSetAssembler_riscv.cpp
! src/hotspot/cpu/riscv/gc/g1/g1BarrierSetAssembler_riscv.hpp
! src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp
! src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.hpp
! src/hotspot/cpu/riscv/gc/shenandoah/shenandoahBarrierSetAssembler_riscv.cpp
! src/hotspot/cpu/riscv/gc/shenandoah/shenandoahBarrierSetAssembler_riscv.hpp
! src/hotspot/cpu/riscv/interp_masm_riscv.cpp
! src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
! src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
! src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp
! src/hotspot/cpu/riscv/stubGenerator_riscv.cpp
! src/hotspot/cpu/riscv/templateInterpreterGenerator_riscv.cpp
! src/hotspot/cpu/riscv/templateTable_riscv.cpp