git: openjdk/jdk: 8309419: RISC-V: Relax register constraint for AddReductionVF & AddReductionVD nodes

[Fei Yang]

Changeset: 7d25bf77
Author:    Gui Cao <gcao at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
Date:      2023-06-06 09:19:27 +0000
URL:       https://git.openjdk.org/jdk/commit/7d25bf7722f6fbe3633dc718adf6f755e354adb9

8309419: RISC-V: Relax register constraint for AddReductionVF & AddReductionVD nodes

Reviewed-by: fyang, luhenry, yzhu

! src/hotspot/cpu/riscv/riscv_v.ad