git: openjdk/jdk: 8308997: RISC-V: Sign extend when comparing 32-bit value with zero instead of testing the sign bit

[Fei Yang]

Changeset: 119994f3
Author:    Dingli Zhang <dzhang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
Date:      2023-05-31 01:31:50 +0000
URL:       https://git.openjdk.org/jdk/commit/119994f3cedab26caa7244e49b58ab6b0b942d91

8308997: RISC-V: Sign extend when comparing 32-bit value with zero instead of testing the sign bit

Co-authored-by: zifeihan <caogui at iscas.ac.cn>
Reviewed-by: fjiang, fyang

! src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp
! src/hotspot/cpu/riscv/interp_masm_riscv.cpp
! src/hotspot/cpu/riscv/interp_masm_riscv.hpp
! src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
! src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
! src/hotspot/cpu/riscv/riscv.ad
! src/hotspot/cpu/riscv/riscv_v.ad
! src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp
! src/hotspot/cpu/riscv/stubGenerator_riscv.cpp
! src/hotspot/cpu/riscv/templateTable_riscv.cpp