git: openjdk/jdk21u: master: 8320280: RISC-V: Avoid passing t0 as temp register to MacroAssembler::lightweight_lock/unlock

[Fei Yang]

Changeset: 3df010f4
Author:    Gui Cao <gcao at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
Date:      2023-11-27 06:00:28 +0000
URL:       https://git.openjdk.org/jdk21u/commit/3df010f444428ecc5ac1efae569dd92134bdf207

8320280: RISC-V: Avoid passing t0 as temp register to MacroAssembler::lightweight_lock/unlock

Backport-of: a6098e438d7c5aa458b37bf94a9cfe706da35d52

! src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp
! src/hotspot/cpu/riscv/c1_LIRGenerator_riscv.cpp
! src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp
! src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.hpp
! src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
! src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp
! src/hotspot/cpu/riscv/interp_masm_riscv.cpp
! src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
! src/hotspot/cpu/riscv/riscv.ad
! src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp