git: openjdk/jdk25u: master: 8367066: RISC-V: refine register selection in MacroAssembler:: decode_klass_not_null

[Fei Yang]

Changeset: 4ad231aa
Branch: master
Author:    Dingli Zhang <dzhang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
Date:      2025-09-13 00:49:59 +0000
URL:       https://git.openjdk.org/jdk25u/commit/4ad231aa5dbbf75bb7cb91a80e8e9323eb1f1c45

8367066: RISC-V: refine register selection in MacroAssembler:: decode_klass_not_null

Backport-of: 0b3a303053d0eb5a98ed3d9df42c659db148b470

! src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
! src/hotspot/cpu/riscv/riscv.ad