[jdk17u-dev] Withdrawn: 8265263: AArch64: Combine vneg with right shift count

[duke]

On Thu, 20 Oct 2022 08:14:59 GMT, Dmitry Chuyko <dchuyko at openjdk.org> wrote:

> This is a performance improvement for AArch64. There are several differences from the original change.
> 
> https://bugs.openjdk.org/browse/JDK-8267356 (Vector API SVE codegen support) is not in 17u, so `UseSVE == 0` parts in predicates are missing/excluded.
> 
> https://bugs.openjdk.org/browse/JDK-8288445 (C2 compilation fails) is a subsequent bugfix already backported in 17u, so some `immI` arguments in rules became `immI_positive`.
> 
> https://bugs.openjdk.org/browse/JDK-8277239 (SIGSEGV in vrshift_reg_maskedNode::emit) is also related to Vector API and is not in 17u, so `!n->as_ShiftV()->is_var_shift()` is replaced by `VectorNode::is_vshift_cnt(n->in(2))`. This substitution may raise doubts.
> 
> Testing: jtreg test/hotspot/jtreg/compiler, tier1, tier2 on aarch64.
> 
> Performance improvements in the added benchmark VectorShiftRight on Graviton 2 for default size=1024 correspond to the original review:
> 
> 
> rShiftByte      16%
> rShiftInt       27%
> rShiftLong      16%
> rShiftShort     20%
> urShiftByte     0%
> urShiftChar     20%
> urShiftInt      27%
> urShiftLong     16%

This pull request has been closed without being integrated.

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PR: https://git.openjdk.org/jdk17u-dev/pull/811