[jmm-dev] [concurrency-interest] Will the real memory read barrier please stand up?

[Stephan Diestelhorst]

On Monday 24 November 2014 09:33:23 Andrew Haley wrote:
> On 24/11/14 00:09, Doug Lea wrote:
> > On 11/20/2014 05:25 AM, Andrew Haley wrote:
> >> On 20/11/14 10:12, Joe Bowbeer wrote:
> >>> As far as I can tell, the cookbook hasn't been updated yet for ARMv8.
> >
> > Mainly out of conservatism given the history of revising ARM and
> > POWER entries multiple times over the years, sometimes based on
> > incomplete or wrong information. It seems worth waiting for multiple
> > validations, including experience from the ARMv8 hotspot port. This
> > is cruel to Andrew (sorry!) but still better than alternatives.
> >
> >>> looks like the following might be helpful in updating the recipes.
> >>>
> >>> http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
> >>
> >> Yes, it looks like the DMB LD is now stronger if, that page is right.
> >>
> >> It'd be nice if someone could point me at the language in the
> >> ARMv8 spec that this derives from.
[..]
> > I'm hoping that someone from ARM answers this.

The usual thing about the group constructions applies with added type
restrictions.

_Shareability and access limitations on the data barrier operations_
The DMB and DSB instructions can each take an optional limitation
argument that specifies:
* The shareability domain over which the instruction must operate. This
  is one of:
  - Full system.
  - Outer Shareable.
  - Inner Shareable.
  - Non-shareable.

* The accesses for which the instruction operates. This is one of:
  - Read and write accesses in Group A and Group B.
  - Write accesses only in Group A and Group B.
  - Read access only in Group A and read and write accesses in Group B.
  Note: This is occasionally referred to as a Load-Load/Store barrier.

> I have communicated with ARM and (although it is implied in the the
> ARMv8 Architecture Reference Manual in a roundabout way) they have
> raised a ticket for clarification in a future update.

Not sure if this is already what you had in mind or whether this is the
"roundabout way", please let me know.  The only issue I have had with
this is that the clarification for the restricted type happens pretty
late. Until then one (I!) too assumed it would only be loads (due to the
name / mnemonic type being "LD").

> They agree that Load-Load|Load-Store is correct.

Yes.

> In the meantime, there is a table of memory barriers on Page 105 of
> the ARMv8 Instruction Set Overview which states this explicitly.

Indeed.

--
Sincerely,
  Stephan

Stephan Diestelhorst
Staff Engineer,
ARM R&D Systems
+44 (0)1223 405662


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