Integrated: RISC-V: Reserve one extra temp register for C2_MacroAssembler::fast_lock

[Fei Yang]

On Wed, 9 Oct 2024 07:12:07 GMT, Fei Yang <fyang at openjdk.org> wrote:

> This is a small improvement for `C2_MacroAssembler::fast_lock`. Currently, we reuse `disp_hdr` (alias of `tmp1Reg`) to hold the loaded current thread id, which means we need to reload markWord from object into displaced_header into `disp_hdr` for later use in recursive lock case. This change simply reserves one extra temp register 'tmp4reg' in order to hold the loaded current thread id like friend `C2_MacroAssembler::fast_lock_lightweight`, which would help avoid such a reloading of markWord. This also fixes one code comment of `C2_MacroAssembler::fast_lock_lightweight`.
> 
> Testing performed on linux-riscv64:
> - [x] make test TEST="hotspot_loom jdk_loom" (release build)
> - [x] make test TEST="hotspot_loom jdk_loom" TEST_VM_OPTS="-XX:+VerifyStack -XX:+VerifyContinuations" (fastdebug build)

This pull request has now been integrated.

Changeset: 98b1b3cb
Author:    Fei Yang <fyang at openjdk.org>
Committer: Patricio Chilano Mateo <pchilanomate at openjdk.org>
URL:       https://git.openjdk.org/loom/commit/98b1b3cbe9cfad21b284bfe07edcf1c4df7dbca6
Stats:     17 lines in 3 files changed: 4 ins; 2 del; 11 mod

RISC-V: Reserve one extra temp register for C2_MacroAssembler::fast_lock

Reviewed-by: pchilanomate

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PR: https://git.openjdk.org/loom/pull/214