[vector]: RFR (XS): Small bug fixes

[Paul Sandoz]

> On Feb 22, 2018, at 10:10 AM, Vladimir Ivanov <vladimir.x.ivanov at oracle.com> wrote:
> 
> http://cr.openjdk.java.net/~vlivanov/panama/vector.fixes.00/
> 
> src/hotspot/cpu/x86/x86.ad:
> 
> While testing the patch proposed by Al Miftah, I spotted a bug in some AD rules for NegVI: src and dst registers can be the same and pxor then overwrites input value.
> 
> 
> src/jdk.incubator.vector/share/classes/jdk/incubator/vector/VectorIntrinsics.java:
> 

A reasonable compromise +1

Paul.

> Mixing vector & scalar memory accesses on a same memory type can be problematic in C2: alias analysis can't detect interference between accesses of different width. That's why aliasing between vector & scalar accesses can get unnoticed and lead to incorrect code being generated.
> 
> Established way to fix that is to put memory barriers in between (e.g., raw unsafe accesses are surrounded by barriers).
> 
> All scalar accesses happens in default implementations and have to fetch backing array first. That's where I decided to put the fence.
> 
> A better place would be in JVM during intrinsification of VI::maybeRebox() (it can take into account whether any vector accesses are performed before putting a barrier), but for now I decided to just put it on Java side using Unsafe.fullFence() to simplify the implementation.
> 
> I considered there's no need in another barrier after, because scalars accesses into backing array are followed by vector box allocation and it should isolate vector accesses happening later.
> 
> Thanks!
> 
> Best regards,
> Vladimir Ivanov