[vector api] Operations on Mask-s

[Vladimir Ivanov]

>> On x86 there are 2 ways to represent masks: (1) as high bits in vector registers >> (pre-AVX512) and (2) as opmask registers (k0-k7). (I believe it's 
similar on ARM
>> with NEON and SVE.)
>>
> 
> Yes, and since SVE has fully predicate (mask) support, we would like to implement it in the mask register way, but need to keep compatible with non-mask Arches.

Speaking of API implementation, I don't see a feasible way to avoid 2 
separate representations of masks on backend side.

Fortunately, it's still possible to keep unified memory layout and do 
proper conversions on heap accesses. That's what x86 already do 
(boolean[] <=> xmm/ymm/zmm, implemented using 
VectorLoadMask/VectorStoreMask nodes) and it works fine.

Moreover, I doubt there's a pressing need to mix 2 representations at 
runtime. Even if there's a desire to represent different shapes with 
different representations, shape conversions are explicit (both in API 
and implementation).

>> C2 doesn't have full AVX512 support yet (e.g., no opmask register support in
>> register allocator) and it was decided to focus on pre-AVX512 model first. So,
>> current implementation represents masks as vectors uniformly across pre-
>> AVX512 and AVX512-capable CPUs. And that's probably the main reason why
>> Mask hasn't got enough attention yet.
>>
> 
> Do you (or anyone else) have any plan to work on opmask register support in register allocator?

I'm not aware of anybody working on it right now. I'll let Intel folks 
comment on their plans. I believe full AVX512 support will be a high 
priority task for subsequent iterations of x86 backend.

Best regards,
Vladimir Ivanov