[vector] Support long addAll() for AVX < 3

[Vladimir Ivanov]

src/hotspot/cpu/x86/x86.ad:
  #ifdef _LP64
  instruct rvadd2L_reduction_reg(rRegL dst, rRegL src1, vecX src2, vecX 
tmp, vecX tmp2) %{
-  predicate(UseAVX > 2);
+  predicate(UseSSE >= 2);

There's no need in the check, since SSE2 support is a requirement on x64.

BTW it would be nice to move 64-bit specific declarations into x86_64.ad.


  instruct rvadd4L_reduction_reg(rRegL dst, rRegL src1, vecY src2, vecY 
tmp, vecY tmp2) %{
-  predicate(UseAVX > 2);
+  predicate(UseAVX >= 1);

Are you sure about AVX1 support? As I see in the docs, 256-bit pshufd 
variant is available since AVX2.

(On a side note, I'm in favor of exclusive range checks: UseAVX > 1 vs 
UseAVX >= 2. The former reads better in x86.ad.)

Best regards,
Vladimir Ivanov

On 21/01/2019 11:32, Viswanathan, Sandhya wrote:
> Hi All,
> 
> Please find below a small patch supporting long addAll for AVX < 3:
> 
> http://cr.openjdk.java.net/~sviswanathan/vectorIntrinsics/longAddReduction/webrev.00/
> 
> Best Regards,
> Sandhya
>