[vector] getting to the edges of the ISAs

[John Rose]

An exercise I’d like to do before the JVMLS is to look again at the ARM and AVX ISAs and see what native operations our API doesn’t cover.  Off the top of my head there are:

1. Snowflake stuff like unsigned multiply, CRC, AES, etc.
2. Specially supported permutations like butterfly (lane-restricted permutation, in “mega lane blocks”), zip/unzip, shuffle/unshuffle (special butterfly).
3. Mask-dependent operations like slice-from-first-set-lane, or compress-all-set-lanes, or (best of all) Sheep-And-Goats (from Hacker’s delight).

Also the 2-D stuff I mentioned earlier.  Plus the Unsafe version of the 1-D and/or 2-D stuff, where the base address is an arbitrary `Object`, and the vector `i` and `j` indexes are raw offsets of type `long`.

Anything else come to mind?

— John

P.S. Something we don’t see at all in today’s vector ISAs, but I remember fondly from the Connection Machine project, is segmented scans.  Those are like reductions, except they present intermediate values at all positions, and like masked reductions, except they reset their presented intermediate values at all mask transitions.  Those operations really come into play with large scale streams, so vector ISAs usually don’t deal with them.

But it would be nice if the vector ISAs had some story for how to build segmented scans, over large-scale workloads, on top of the operations on fixed-length vectors.