[vectorIntrinsics] RFR: 8254826: Add reduction nodes implementation for Arm SVE

[Ningsheng Jian]

On Thu, 15 Oct 2020 10:52:06 GMT, Dongbo He <dongbohe at openjdk.org> wrote:

> Contributed-by: <wanghuang3 at huawei.com>, <hexuejin2 at huawei.com>
> 
> Add reduction nodes support for Arm SVE. Add the backend codegen for nodes like "AndReductionVNode" "OrReductionVNode"
> "XorReductionVNode" "MaxReductionVNode" "MinReductionVNode" .

src/hotspot/cpu/aarch64/aarch64_sve_ad.m4 line 697:

> 695: // vector or reduction
> 696: REDUCE_OR_EXT(reduce_orB, OrReductionV, iRegINoSp, iRegIorL2I, B, T_BYTE,  sxtb)
> 697: REDUCE_OR_EXT(reduce_orS, OrReductionV, iRegINoSp, iRegIorL2I, H, T_SHORT,  sxth)

nit: no need to add extra space before sxth. :-)

src/hotspot/cpu/aarch64/aarch64_sve_ad.m4 line 747:

> 745: // vector xor reduction
> 746: REDUCE_XOR_EXT(reduce_eorB, XorReductionV, iRegINoSp, iRegIorL2I, B, T_BYTE,  sxtb)
> 747: REDUCE_XOR_EXT(reduce_eorS, XorReductionV, iRegINoSp, iRegIorL2I, H, T_SHORT,  sxth)

remove extra space before sxth?

src/hotspot/cpu/aarch64/aarch64_sve.ad line 1214:

> 1212:             (n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE));
> 1213:   match(Set dst (MaxReductionV src1 src2));
> 1214:   effect(TEMP_DEF dst, TEMP tmp);

Since the cmp instruction will generate condition code, I think you will need effect to KILL rFlagsReg here and other
min/max reduction implementations.

-------------

PR: https://git.openjdk.java.net/panama-vector/pull/13