[vectorIntrinsics] RFR: Optimize mem barriers for ByteBuffer cases [v6]

[Vladimir Ivanov]

On Wed, 4 Aug 2021 21:06:07 GMT, Radoslaw Smogura <github.com+7535718+rsmogura at openjdk.org> wrote:

> for a store we could assign result of StoreVector to two slices raw, and byte[] in a memory merge node,

I don't see how it could work with the alias analysis (as it is implemented now). 
Every memory slice is "flattened" into a unique slice which doesn't alias with anything except the one represented with `TypePtr::BOTTOM`. What you suggest implies that some slices start to alias with raw memory. It will break the existing logic unless you find a smart way to fix it.   

> for a load, we could consume the whole memory as input, instead of a single slice.

Still, you need to be very cautious about the alias index being assigned to the "wide" memory slice of mixed/mismatched access.  Also, the logic which inserts anti-dependencies in the graph has to be taught about the aliasing slices. 

Overall, it looks error-prone and it wouldn't necessarily lead to a simpler IR (and better generated code) compared to CPU membars.

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PR: https://git.openjdk.java.net/panama-vector/pull/104