[vectorIntrinsics] RFR: Merge panama-vector:master
Jatin Bhateja
jbhateja at openjdk.java.net
Tue Aug 17 06:53:45 UTC 2021
On Mon, 16 Aug 2021 16:41:11 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:
> Following two files have merge conflicts
> - src/hotspot/cpu/aarch64/aarch64_sve_ad.m4
> - src/hotspot/cpu/aarch64/aarch64_sve.ad
Hi @nsjian / @theRealELiu / @XiaohongGong
Following diff fixes this merge and hotspot builds successfully.
Kindly validate the changes. Certain mainline commits are needed for vectorIntrinsics+mask work for X86.
diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad
index 430d7d8460c..d5ce5e10914 100644
--- a/src/hotspot/cpu/aarch64/aarch64.ad
+++ b/src/hotspot/cpu/aarch64/aarch64.ad
@@ -1295,6 +1295,30 @@ public:
};
};
+ static inline BasicType vector_element_basic_type(const MachNode* n) {
+ const TypeVect* vt = n->bottom_type()->is_vect();
+ return vt->element_basic_type();
+ }
+
+ static inline BasicType vector_element_basic_type(const MachNode* use, const MachOper* opnd) {
+ int def_idx = use->operand_index(opnd);
+ Node* def = use->in(def_idx);
+ const TypeVect* vt = def->bottom_type()->is_vect();
+ return vt->element_basic_type();
+ }
+
+ static inline uint vector_length(const MachNode* n) {
+ const TypeVect* vt = n->bottom_type()->is_vect();
+ return vt->length();
+ }
+
+ static inline uint vector_length(const MachNode* use, const MachOper* opnd) {
+ int def_idx = use->operand_index(opnd);
+ Node* def = use->in(def_idx);
+ const TypeVect* vt = def->bottom_type()->is_vect();
+ return vt->length();
+ }
+
bool is_CAS(int opcode, bool maybe_volatile);
// predicates controlling emit of ldr<x>/ldar<x> and associated dmb
diff --git a/src/hotspot/cpu/aarch64/aarch64_sve.ad b/src/hotspot/cpu/aarch64/aarch64_sve.ad
index a85d89467db..3d7a1f72afd 100644
--- a/src/hotspot/cpu/aarch64/aarch64_sve.ad
+++ b/src/hotspot/cpu/aarch64/aarch64_sve.ad
@@ -190,16 +190,10 @@ instruct loadV(vReg dst, vmemA mem) %{
format %{ "sve_ldr $dst, $mem\t# vector (sve)" %}
ins_encode %{
FloatRegister dst_reg = as_FloatRegister($dst$$reg);
-<<<<<<< HEAD
BasicType bt = vector_element_basic_type(this);
loadStoreA_predicated(C2_MacroAssembler(&cbuf), false, dst_reg, ptrue,
bt, bt, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
-=======
- loadStoreA_predicate(C2_MacroAssembler(&cbuf), false, dst_reg, ptrue,
- Matcher::vector_element_basic_type(this), $mem->opcode(),
- as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
->>>>>>> 82688258f676e6be8a603f6ab744d52728e3478b
%}
ins_pipe(pipe_slow);
%}
@@ -343,7 +337,6 @@ instruct storeV_partial(vReg src, vmemA mem, pRegGov pTmp, rFlagsReg cr) %{
BasicType bt = vector_element_basic_type(this, $src);
__ sve_whilelo_zr_imm(as_PRegister($pTmp$$reg), __ elemType_to_regVariant(bt), vector_length(this, $src));
FloatRegister src_reg = as_FloatRegister($src$$reg);
-<<<<<<< HEAD
loadStoreA_predicated(C2_MacroAssembler(&cbuf), true, src_reg,
as_PRegister($pTmp$$reg), bt, bt, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
@@ -383,11 +376,6 @@ instruct reinterpretResize(vReg dst, vReg src, pRegGov pTmp, rFlagsReg cr) %{
__ sve_dup(as_FloatRegister($dst$$reg), __ B, 0);
__ sve_sel(as_FloatRegister($dst$$reg), __ B, as_PRegister($pTmp$$reg),
as_FloatRegister($src$$reg), as_FloatRegister($dst$$reg));
-=======
- loadStoreA_predicate(C2_MacroAssembler(&cbuf), true, src_reg, ptrue,
- Matcher::vector_element_basic_type(this, $src), $mem->opcode(),
- as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
->>>>>>> 82688258f676e6be8a603f6ab744d52728e3478b
%}
ins_pipe(pipe_slow);
%}
@@ -691,13 +679,8 @@ instruct vmin(vReg dst_src1, vReg src2) %{
ins_cost(SVE_COST);
format %{ "sve_min $dst_src1, $dst_src1, $src2\t # vector (sve)" %}
ins_encode %{
-<<<<<<< HEAD
BasicType bt = vector_element_basic_type(this);
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
-=======
- BasicType bt = Matcher::vector_element_basic_type(this);
- Assembler::SIMD_RegVariant size = elemType_to_regVariant(bt);
->>>>>>> 82688258f676e6be8a603f6ab744d52728e3478b
if (is_floating_point_type(bt)) {
__ sve_fmin(as_FloatRegister($dst_src1$$reg), size,
ptrue, as_FloatRegister($src2$$reg));
@@ -716,13 +699,8 @@ instruct vmax(vReg dst_src1, vReg src2) %{
ins_cost(SVE_COST);
format %{ "sve_max $dst_src1, $dst_src1, $src2\t # vector (sve)" %}
ins_encode %{
-<<<<<<< HEAD
BasicType bt = vector_element_basic_type(this);
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
-=======
- BasicType bt = Matcher::vector_element_basic_type(this);
- Assembler::SIMD_RegVariant size = elemType_to_regVariant(bt);
->>>>>>> 82688258f676e6be8a603f6ab744d52728e3478b
if (is_floating_point_type(bt)) {
__ sve_fmax(as_FloatRegister($dst_src1$$reg), size,
ptrue, as_FloatRegister($src2$$reg));
diff --git a/src/hotspot/cpu/aarch64/aarch64_sve_ad.m4 b/src/hotspot/cpu/aarch64/aarch64_sve_ad.m4
index 22a0487f2ac..3d9087a8035 100644
--- a/src/hotspot/cpu/aarch64/aarch64_sve_ad.m4
+++ b/src/hotspot/cpu/aarch64/aarch64_sve_ad.m4
@@ -193,16 +193,10 @@ instruct loadV(vReg dst, vmemA mem) %{
format %{ "sve_ldr $dst, $mem\t# vector (sve)" %}
ins_encode %{
FloatRegister dst_reg = as_FloatRegister($dst$$reg);
-<<<<<<< HEAD
BasicType bt = vector_element_basic_type(this);
loadStoreA_predicated(C2_MacroAssembler(&cbuf), false, dst_reg, ptrue,
bt, bt, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
-=======
- loadStoreA_predicate(C2_MacroAssembler(&cbuf), false, dst_reg, ptrue,
- Matcher::vector_element_basic_type(this), $mem->opcode(),
- as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
->>>>>>> 82688258f676e6be8a603f6ab744d52728e3478b
%}
ins_pipe(pipe_slow);
%}
@@ -280,15 +274,9 @@ instruct storeV_partial(vReg src, vmemA mem, pRegGov pTmp, rFlagsReg cr) %{
BasicType bt = vector_element_basic_type(this, $src);
__ sve_whilelo_zr_imm(as_PRegister($pTmp$$reg), __ elemType_to_regVariant(bt), vector_length(this, $src));
FloatRegister src_reg = as_FloatRegister($src$$reg);
-<<<<<<< HEAD
loadStoreA_predicated(C2_MacroAssembler(&cbuf), true, src_reg,
as_PRegister($pTmp$$reg), bt, bt, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
-=======
- loadStoreA_predicate(C2_MacroAssembler(&cbuf), true, src_reg, ptrue,
- Matcher::vector_element_basic_type(this, $src), $mem->opcode(),
- as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
->>>>>>> 82688258f676e6be8a603f6ab744d52728e3478b
%}
ins_pipe(pipe_slow);
%}dnl
@@ -482,13 +470,8 @@ instruct vmin(vReg dst_src1, vReg src2) %{
ins_cost(SVE_COST);
format %{ "sve_min $dst_src1, $dst_src1, $src2\t # vector (sve)" %}
ins_encode %{
-<<<<<<< HEAD
BasicType bt = vector_element_basic_type(this);
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
-=======
- BasicType bt = Matcher::vector_element_basic_type(this);
- Assembler::SIMD_RegVariant size = elemType_to_regVariant(bt);
->>>>>>> 82688258f676e6be8a603f6ab744d52728e3478b
if (is_floating_point_type(bt)) {
__ sve_fmin(as_FloatRegister($dst_src1$$reg), size,
ptrue, as_FloatRegister($src2$$reg));
@@ -507,13 +490,8 @@ instruct vmax(vReg dst_src1, vReg src2) %{
ins_cost(SVE_COST);
format %{ "sve_max $dst_src1, $dst_src1, $src2\t # vector (sve)" %}
ins_encode %{
-<<<<<<< HEAD
BasicType bt = vector_element_basic_type(this);
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
-=======
- BasicType bt = Matcher::vector_element_basic_type(this);
- Assembler::SIMD_RegVariant size = elemType_to_regVariant(bt);
->>>>>>> 82688258f676e6be8a603f6ab744d52728e3478b
if (is_floating_point_type(bt)) {
__ sve_fmax(as_FloatRegister($dst_src1$$reg), size,
ptrue, as_FloatRegister($src2$$reg));
-------------
PR: https://git.openjdk.java.net/panama-vector/pull/111
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