[vectorIntrinsics+mask] RFR: 8266287: Basic mask IR implementation for the Vector API masking feature support [v3]

[Xiaohong Gong]

On Wed, 23 Jun 2021 02:05:16 GMT, Xiaohong Gong <xgong at openjdk.org> wrote:

>> Box/Unbox are macro nodes which encapsulates value, in this case the mask value is contained either in  a a vector or a predicate register. This should ideally not be disturbing the box's vector type() I think.
>
> Did you implement the vector mask IRs with `TypeVectMask` type in backend? I made a workaround to make sure the tests can pass with this patch but without any backend implementation for AVX-512/SVE. Please see the change in `type.cpp`:
> 
> const TypeVect *TypeVect::makemask(const Type* elem, uint length) {
>   if (Matcher::has_predicated_vectors() &&
>       // TODO: remove this condition once the backend is supported.
>       // Workround to make tests pass on AVX-512/SVE when predicate is not supported.
>       // Could be removed once the backend is supported.
>       Matcher::match_rule_supported_vector_masked(Op_StoreVectorMasked, MaxVectorSize, T_BOOLEAN)) {
>     const TypeVect* mtype = Matcher::predicate_reg_type(elem, length);
>     return (TypeVect*)(const_cast<TypeVect*>(mtype))->hashcons();
>   } else {
> 
> The `TypeVectMask` can only be made successfully when the backend has implemented masked `Op_StoreVectorMasked`. This is just a workaround that would be removed once the AVX-512 add the backend implementation for all mask/masked IRs.

>From the crash log, I guess the issue happens for a `PhiNode` with vector masks as its values. Assume one of its value is a `VectorUnboxNode` with `TypeVect` while others are mask nodes with `TypeVectMask`, then the crash can happen when the compiler try to decide the final type of the `PhiNode`. Please correct me if I misunderstand it. Thanks!

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PR: https://git.openjdk.java.net/panama-vector/pull/78