[vectorIntrinsics] RFR: RFC: Vector API masking support proposal for Arm SVE [v3]

[Xiaohong Gong]

On Fri, 12 Mar 2021 13:35:30 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

>> Xiaohong Gong has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Add mask support for masked binary operations
>
> src/hotspot/cpu/aarch64/aarch64_sve.ad line 377:
> 
>> 375: instruct vmask2vector(vReg dst, pRegGov pg) %{
>> 376:   predicate(UseSVE > 0);
>> 377:   match(Set dst (MaskToVector pg));
> 
> We already have VectorLoadMask and VectorStoreMask nodes which have same semantics as Mask2Vector and Vector2Mask operation. Can you please elaborate the need for these new nodes.

Thanks for your comment about this. `VectorLoadMask` and `VectorStoreMask` are vector nodes that have the `TypeVect` type, while `Vector2Mask` is a mask node that have the `TypeVMask` type.  For SVE, the two new added nodes are used for conversions between vector register and predicate register, e.g. `Mask2Vector` for `predicate -> vector` and `Vector2Mask` for `vector -> predicate`. Yes, it seems `VectorLoadMask` and `VectorStoreMask` can match the same requirements like what have been done in the AVX-512 patch. However, in our whole proposal, we defined different IRs to separate vector and mask operations. I think the main conflict is the IR part for mask. And it's better to get a final solution to the different operations together for SVE and AVX-512.

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PR: https://git.openjdk.java.net/panama-vector/pull/40