[vectorIntrinsics] RFR: RFC: Vector API masking support proposal for Arm SVE [v3]

[Xiaohong Gong]

On Fri, 12 Mar 2021 15:10:27 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

>> Xiaohong Gong has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Add mask support for masked binary operations
>
> src/hotspot/cpu/aarch64/aarch64_sve.ad line 1301:
> 
>> 1299:   ins_encode %{
>> 1300:     // Load mask values which are boolean type, and extend them to the
>> 1301:     // expected vector element type.
> 
> Isn't this same as existing VectorLoadMaskNode ?

I'm not sure whether this can benefit AVX-512 masking load. It loads the values from boolean memory and extends the boolean values to relative other basic types (short,int,long). Different with AVX-512, SVE predicate register controls the vector activity depending on the element type, i.e. it uses 1-bit to control a byte lane, and 2-bits for a short lane, and 4-bits for an int lane, and so on. The type extending/narrowing between real basic type and boolean is always needed. As SVE provides a single instruction to implement the `load+extend` function, we don't need to load values and extend them with external instructions. So that's what the new added node used to do. Maybe a better name for it is `LoadVectorExtendNode`.

> src/hotspot/cpu/aarch64/aarch64_sve.ad line 1315:
> 
>> 1313:   predicate(UseSVE > 0);
>> 1314:   match(Set mem (StoreVectorMask mem src));
>> 1315:   format %{ "sve_st1b $src, $mem\t # store vector mask (sve)" %}
> 
> Same comments as above, how different is this from existing VectorStoreMaskNode

The same with `LoadVectorMaskNode`.

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PR: https://git.openjdk.java.net/panama-vector/pull/40