[vectorIntrinsics] RFR: 8285281: [x86] Add C2 mid-end and back-end implementation for COMPRESS_BITS and EXPAND_BITS operations [v3]

[Xiaohong Gong]

On Tue, 26 Apr 2022 10:46:59 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

>> Summary of changes:
>> - Patch intrinsifies following newly added Java SE APIs
>>    1.  Integer.compress  
>>    2.  Integer.expand
>>    3.  Long.compress
>>    4.  Long.expand
>> - Adds C2 IR nodes and corresponding ideal transformations for new operations.
>> - Inline expansion of  new vector operations COMPRESS_BITS and  EXPAND_BITS are performed using their scalar counterparts and lane insertion/extraction operations.
>> - Performance of JIT sequence generated using above approach vs directly vectorizing scalar algorithm using existing vector APIs is within in +/-%10 range depending on the width of the operation, since X86 offers direct instructions PEXT/PDEP for parallel bit extraction and deposition operations hence performance of scalar loop is always superior to corresponding vector  operations.
>> - Adds an  IR framework based test to validate newly introduced IR transformations.
>> 
>> Kindly review and share your feedback.
>> 
>> Best Regards,
>> Jatin
>
> Jatin Bhateja has updated the pull request incrementally with one additional commit since the last revision:
> 
>   8285281: Review comments resolved.

src/hotspot/share/opto/vectorIntrinsics.cpp line 589:

> 587:   } else if (VectorNode::is_bitshuffle_opcode(sopc) && !Matcher::match_rule_supported_vector(sopc, num_elem, elem_bt)) {
> 588:     operation = gen_bitshuffle_operation(opc, elem_bt, num_elem, opd1, opd2);
> 589:   } else {

I'm afraid that you should add the `Op_CompressBitsV` and `Op_ExpandBitsV` node creation in `VectorNode::make()`. If the backend support these two ops, the jvm crashes due to missing creation of these two nodes. I met the issue when I try to support the backend for ARM SVE:

Internal Error (panama-vector/src/hotspot/share/opto/vectornode.cpp:657), pid=152820, tid=152852
#  fatal error: Missed vector creation for 'CompressBitsV'

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PR: https://git.openjdk.java.net/panama-vector/pull/195