[vectorIntrinsics+fp16] RFR: 8305563: [vectorapi]: Initial aarch64 backend implementation for FP16 operations [v2]

[Andrew Haley]

On Tue, 27 Jun 2023 10:13:41 GMT, Bhavana Kilambi <bkilambi at openjdk.org> wrote:

>> This patch adds aarch64 (Neon and SVE) backend implementation for the following FP16 operations for which C2 support was added in the commit https://github.com/openjdk/panama-vector/commit/7460d9327aac7d1d2ba6aed4e7137a417dbf6a97 -
>> 
>> Unary operations : AbsVHF, NegVHF
>> Binary operations : AddVHF, SubVHF, MulVHF, DivVHF
>> Ternary operations : AddReductionVHF, FmaVHF
>> Conversion operations : VectorCastHF2D, VectorCastD2HF
>> 
>> Some of these operations on Neon machines, require features "fphp" and "asimdhp" to be available. Feature detection for these features have also been added.
>
> Bhavana Kilambi has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Addressed review comments

Otherwise fine.

src/hotspot/cpu/aarch64/assembler_aarch64.hpp line 2724:

> 2722:                      int op1, int op2, int op3);
> 2723: 
> 2724: // Advanced SIMD three same

Suggestion:

    // Advanced SIMD three same

    void adv_simd_three_same(Instruction_aarch64 &current_insn, FloatRegister Vd,
                     SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm,
                     int op1, int op2, int op3);


Always match names with names in the Architecture Reference Manual where we can.

-------------

PR Review: https://git.openjdk.org/panama-vector/pull/217#pullrequestreview-1501374765
PR Review Comment: https://git.openjdk.org/panama-vector/pull/217#discussion_r1244010978