[sw-dev] Project proposal: RISC-V port

[Bruce Hoult]

In two months you can have your hands on a quad core 1.5 GHz dev board with
8 GB RAM.

Though RISC-V is so easy to emulate that qemu on a recent i7 will probably
be as fast or faster. (Using a root FS, chroot and binfmt_misc to set qemu
as the interpreter for RISC-V ELF)

On Thu, Feb 8, 2018 at 9:23 PM, Andrew Haley <aph at redhat.com> wrote:

> On 08/02/18 17:20, Bruce Hoult wrote:
> > Having been involved in porting Microsoft's CoreCLR JIT to ARM (for Tizen
> > 4.0) I'd say that's an underestimate, unless OpenJDK is somehow far
> better
> > written.
>
> We have done it before.  It's a lower bound.
>
> Mind you, unless there's some real hardware available it'll take a lot
> longer.  For AArch64 we wrote a tiny simulator and lined it in to the
> HotSpot runtime so that everything except the JIT-generated code ran
> as native optimized x86-64 code.  That helped a lot: if you had to run
> the entire JVM in emulation you'd die waiting for it to get as far as
> generating the interpreter.
>
> --
> Andrew Haley
> Java Platform Lead Engineer
> Red Hat UK Ltd. <https://www.redhat.com>
> EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671
>
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