From duke at openjdk.java.net  Wed Dec  1 01:48:01 2021
From: duke at openjdk.java.net (kuaiwei)
Date: Wed, 1 Dec 2021 01:48:01 GMT
Subject: [riscv-port] RFR: 8277968: riscv: Detect vector extension with
 vcsr [v2]
In-Reply-To: <-NT5UlFnkXOx4doj-ZlI5cQvVb1aFIkIOVs9H2dFp1E=.2aeb817f-9ba3-4b16-88e8-44ae7d89e214@github.com>
References: <lGp09-9gJ25b4ug7q5loY6mPeiqNj4t4LXiS61VS_ek=.85adc733-85db-46f9-9d9b-544e524cc970@github.com>
 <-NT5UlFnkXOx4doj-ZlI5cQvVb1aFIkIOVs9H2dFp1E=.2aeb817f-9ba3-4b16-88e8-44ae7d89e214@github.com>
Message-ID: <cv4PMJpQM4MgZaY8SIoZ1-nvKlCv1ExINFWqyNAQuE0=.963405e3-12ca-4566-b511-6c5235f53300@github.com>

On Tue, 30 Nov 2021 08:04:52 GMT, kuaiwei <duke at openjdk.java.net> wrote:

>> UseRVV could cause crash on D1 board(RISCV-C906).
>> 
>> It seems that though the D1 board is equipped with RVV-0.7.1[1] . In our test, VLENB CSR can return value of 16 on D1 board. So JDK will assume it can support RVV extension and crash in vector instructions when  UseRVV is enabled.  
>> 
>> RVV-0.9 and above[2] introduce a new VCSR CSR register, it will raise SIGILL on D1 board. So we can check it to detect vext support.
>> 
>> 
>> [1] https://github.com/riscv/riscv-v-spec/blob/0a24d0f61b5cd3f1f9265e8c40ab211daa865ede/v-spec.adoc#vector-extension-programmers-model
>> [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-extension-programmers-model
>
> kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.

> 

I'm not sure about it. But it looks we can not check cpu arch with /proc/cpuinfo. It's dependent on os implementation.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/18

From xlinzheng at openjdk.java.net  Wed Dec  1 02:46:11 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Wed, 1 Dec 2021 02:46:11 GMT
Subject: [riscv-port] RFR: 8278033: riscv: Fix MacroAssembler::atomic_incw:
 store condition instruction has wrong operand order
Message-ID: <oTHgPnarOVfZgrPw7dB-IU7JRe0j33_uCp9gTQPekWY=.491a0f26-162c-47d9-943b-5621844cf482@github.com>

This is a trivial fix for this typo. This could reproduce before JDK18 by using `-XX:+PrintBiasedLockingStatistics`; however, after the removal of BiasedLocking, this function has no usage now. But we might fix it as well for future usage since it is a quite fundamental function. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/11)

-------------

Commit messages:
 - Fix store condition: instruction has wrong operand order

Changes: https://git.openjdk.java.net/riscv-port/pull/19/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=19&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278033
  Stats: 1 line in 1 file changed: 0 ins; 0 del; 1 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/19.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/19/head:pull/19

PR: https://git.openjdk.java.net/riscv-port/pull/19

From xlinzheng at openjdk.java.net  Wed Dec  1 02:48:14 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Wed, 1 Dec 2021 02:48:14 GMT
Subject: [riscv-port] RFR: 8278034: riscv: Fix callee-saved float register
 definitions: should be SOE
Message-ID: <WJ2SqNNlc25vlYiQQ9UEmvf2AxXm0WHg4SaR6GC2X7Y=.438df9a4-84b6-4ab7-9288-44c6e1fa9910@github.com>

There are unnecessary float register spills before leaf calls and it seems that callee-saved float registers' definitions should be SOE so the register allocator may firstly use these SOE registers as allocation candidates to prevent spills before leaf calls. I have looked through F8-F9, F18-F27 usages and found they are not used in any stub so it could be safe. Tested all cases. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/13)

This fix is nearly the same as [JDK-8253048](https://bugs.openjdk.java.net/browse/JDK-8253048)'s [PR](https://github.com/openjdk/jdk/pull/129) on the aarch64 platform and receives an identical result.

-------------

Commit messages:
 - Fix callee-saved float register definitions: should be SOE

Changes: https://git.openjdk.java.net/riscv-port/pull/20/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=20&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278034
  Stats: 27 lines in 1 file changed: 0 ins; 0 del; 27 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/20.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/20/head:pull/20

PR: https://git.openjdk.java.net/riscv-port/pull/20

From fyang at openjdk.java.net  Wed Dec  1 02:56:48 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Wed, 1 Dec 2021 02:56:48 GMT
Subject: [riscv-port] RFR: 8278033: riscv: Fix MacroAssembler::atomic_incw:
 store condition instruction has wrong operand order
In-Reply-To: <oTHgPnarOVfZgrPw7dB-IU7JRe0j33_uCp9gTQPekWY=.491a0f26-162c-47d9-943b-5621844cf482@github.com>
References: <oTHgPnarOVfZgrPw7dB-IU7JRe0j33_uCp9gTQPekWY=.491a0f26-162c-47d9-943b-5621844cf482@github.com>
Message-ID: <jPRcheYsbZLutkMjKKI7vmRJsyvYrL9XASmHZeQ-2Xg=.5b957928-33e8-4b47-b90e-6a4c79a24a64@github.com>

On Wed, 1 Dec 2021 02:40:31 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> This is a trivial fix for this typo. This could reproduce before JDK18 by using `-XX:+PrintBiasedLockingStatistics`; however, after the removal of BiasedLocking, this function has no usage now. But we might fix it as well for future usage since it is a quite fundamental function. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/11)

Looks good and trivial. Thanks.

-------------

Marked as reviewed by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/19

From xlinzheng at openjdk.java.net  Wed Dec  1 03:05:47 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Wed, 1 Dec 2021 03:05:47 GMT
Subject: [riscv-port] Integrated: 8278033: riscv: Fix
 MacroAssembler::atomic_incw: store condition instruction has wrong operand
 order
In-Reply-To: <oTHgPnarOVfZgrPw7dB-IU7JRe0j33_uCp9gTQPekWY=.491a0f26-162c-47d9-943b-5621844cf482@github.com>
References: <oTHgPnarOVfZgrPw7dB-IU7JRe0j33_uCp9gTQPekWY=.491a0f26-162c-47d9-943b-5621844cf482@github.com>
Message-ID: <i9hCvmyvdtTOVFGXHW4VHnpw4kNF_Z6oTbTQGLv4DnY=.991df9c1-9de2-4057-9028-68099f474557@github.com>

On Wed, 1 Dec 2021 02:40:31 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> This is a trivial fix for this typo. This could reproduce before JDK18 by using `-XX:+PrintBiasedLockingStatistics`; however, after the removal of BiasedLocking, this function has no usage now. But we might fix it as well for future usage since it is a quite fundamental function. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/11)

This pull request has now been integrated.

Changeset: 8239cbb3
Author:    Xiaolin Zheng <xlinzheng at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/8239cbb38e3ea0e1b4c840294ad9578ef687d2d5
Stats:     1 line in 1 file changed: 0 ins; 0 del; 1 mod

8278033: riscv: Fix MacroAssembler::atomic_incw: store condition instruction has wrong operand order

Reviewed-by: fyang

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/19

From fyang at openjdk.java.net  Wed Dec  1 07:02:48 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Wed, 1 Dec 2021 07:02:48 GMT
Subject: [riscv-port] RFR: 8278034: riscv: Fix callee-saved float register
 definitions: should be SOE
In-Reply-To: <WJ2SqNNlc25vlYiQQ9UEmvf2AxXm0WHg4SaR6GC2X7Y=.438df9a4-84b6-4ab7-9288-44c6e1fa9910@github.com>
References: <WJ2SqNNlc25vlYiQQ9UEmvf2AxXm0WHg4SaR6GC2X7Y=.438df9a4-84b6-4ab7-9288-44c6e1fa9910@github.com>
Message-ID: <I1I5B_tSKlTZEuv1dKvPlWFVPVlgT4PjZSQiUPSn8kM=.0eccfbb7-d357-4695-be35-36d45e8dc51b@github.com>

On Wed, 1 Dec 2021 02:43:12 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> There are unnecessary float register spills before leaf calls and it seems that callee-saved float registers' definitions should be SOE so the register allocator may firstly use these SOE registers as allocation candidates to prevent spills before leaf calls. I have looked through F8-F9, F18-F27 usages and found they are not used in any stub so it could be safe. Tested all cases. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/13)
> 
> This fix is nearly the same as [JDK-8253048](https://bugs.openjdk.java.net/browse/JDK-8253048)'s [PR](https://github.com/openjdk/jdk/pull/129) on the aarch64 platform and receives an identical result.

Thanks for looking at this. Looks good.

-------------

Marked as reviewed by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/20

From xlinzheng at openjdk.java.net  Wed Dec  1 07:02:48 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Wed, 1 Dec 2021 07:02:48 GMT
Subject: [riscv-port] RFR: 8278034: riscv: Fix callee-saved float register
 definitions: should be SOE
In-Reply-To: <WJ2SqNNlc25vlYiQQ9UEmvf2AxXm0WHg4SaR6GC2X7Y=.438df9a4-84b6-4ab7-9288-44c6e1fa9910@github.com>
References: <WJ2SqNNlc25vlYiQQ9UEmvf2AxXm0WHg4SaR6GC2X7Y=.438df9a4-84b6-4ab7-9288-44c6e1fa9910@github.com>
Message-ID: <N17ApvxmLB8dG0um1tMZrKu6wppx_z9iXIPitDPJBZw=.b5655472-d800-41a2-a26c-25d54daf0b01@github.com>

On Wed, 1 Dec 2021 02:43:12 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> There are unnecessary float register spills before leaf calls and it seems that callee-saved float registers' definitions should be SOE so the register allocator may firstly use these SOE registers as allocation candidates to prevent spills before leaf calls. I have looked through F8-F9, F18-F27 usages and found they are not used in any stub so it could be safe. Tested all cases. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/13)
> 
> This fix is nearly the same as [JDK-8253048](https://bugs.openjdk.java.net/browse/JDK-8253048)'s [PR](https://github.com/openjdk/jdk/pull/129) on the aarch64 platform and receives an identical result.

Thank you for reviewing this -

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/20

From xlinzheng at openjdk.java.net  Wed Dec  1 07:06:56 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Wed, 1 Dec 2021 07:06:56 GMT
Subject: [riscv-port] Integrated: 8278034: riscv: Fix callee-saved float
 register definitions: should be SOE
In-Reply-To: <WJ2SqNNlc25vlYiQQ9UEmvf2AxXm0WHg4SaR6GC2X7Y=.438df9a4-84b6-4ab7-9288-44c6e1fa9910@github.com>
References: <WJ2SqNNlc25vlYiQQ9UEmvf2AxXm0WHg4SaR6GC2X7Y=.438df9a4-84b6-4ab7-9288-44c6e1fa9910@github.com>
Message-ID: <S-NjM6cwAo4CKssfbGe9iNrxtKMfLDIMr8KOLAdnYF4=.3d77c13d-9392-489f-866a-2e6794524796@github.com>

On Wed, 1 Dec 2021 02:43:12 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> There are unnecessary float register spills before leaf calls and it seems that callee-saved float registers' definitions should be SOE so the register allocator may firstly use these SOE registers as allocation candidates to prevent spills before leaf calls. I have looked through F8-F9, F18-F27 usages and found they are not used in any stub so it could be safe. Tested all cases. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/13)
> 
> This fix is nearly the same as [JDK-8253048](https://bugs.openjdk.java.net/browse/JDK-8253048)'s [PR](https://github.com/openjdk/jdk/pull/129) on the aarch64 platform and receives an identical result.

This pull request has now been integrated.

Changeset: f64057e0
Author:    Xiaolin Zheng <xlinzheng at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/f64057e0d59421470d10dcb64fc626d5bf8999a0
Stats:     27 lines in 1 file changed: 0 ins; 0 del; 27 mod

8278034: riscv: Fix callee-saved float register definitions: should be SOE

Reviewed-by: fyang

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/20

From xlinzheng at openjdk.java.net  Wed Dec  1 07:45:46 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Wed, 1 Dec 2021 07:45:46 GMT
Subject: [riscv-port] RFR: 8277890: riscv: fix the infinite LR/SC loop in
 BarrierSetAssembler::eden_allocate
In-Reply-To: <hhdB7LVyeNVwXWou550qw6AiJ47mv7GhWjwOJY0gW5k=.741e4ab0-b9ca-42ab-a248-bd756ecbf704@github.com>
References: <hhdB7LVyeNVwXWou550qw6AiJ47mv7GhWjwOJY0gW5k=.741e4ab0-b9ca-42ab-a248-bd756ecbf704@github.com>
Message-ID: <uPLjG2DPfCva7N_Yh-DKactl48J3hAaVFUvxT33eaQA=.81796a03-3b81-4dd7-aad5-46def4f49154@github.com>

On Mon, 29 Nov 2021 15:06:51 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> This bug can be reproduced by `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1 -version` on the unmatched board where this command will hang. The reason is that the implementation of load reserved/store conditional loop in BarrierSetAssembler::eden_allocate breaks the RISC-V Atomic extension spec:
> 
> For the
> sequence to be guaranteed to eventually succeed, the dynamic code executed between the LR and
> SC instructions can only contain other instructions from the base \I" subset, excluding loads, stores,
> backward jumps or taken backward branches, FENCE, FENCE.I, and SYSTEM instructions.
> 
> It may cause an unspecified behaviour depends on specific hardware implementations.

Thank you for fixing this. Qemu and C910 cannot reveal this issue so I didn't notice it.  :-(   
I just tested this `-XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1` on both a D1 and an unleashed board, and this issue was reproduced without this patch.

No need to reply -- it is just a comment.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/17

From yadongwang at openjdk.java.net  Wed Dec  1 08:02:11 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Wed, 1 Dec 2021 08:02:11 GMT
Subject: [riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine
 flags register in C2
Message-ID: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>

There are non-allocatable registers t0 and t1 in C2, frequently used as temporary registers for common code snipptes. Meanwhile, C2 use t1 as the flags register, so that many instructs using t1 as a temporary register must declare the data flow effect of t1 which is not part of a match rule. So we can reserve t2 and use it as the machine flags register in C2 instead, to reduce the probability of misuse of t1 without declaring the data flow effect.

-------------

Commit messages:
 - 8278041: riscv: Use t2 as the dedicated machine flags register in C2

Changes: https://git.openjdk.java.net/riscv-port/pull/21/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=21&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278041
  Stats: 144 lines in 4 files changed: 3 ins; 24 del; 117 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/21.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/21/head:pull/21

PR: https://git.openjdk.java.net/riscv-port/pull/21

From fyang at openjdk.java.net  Wed Dec  1 08:39:45 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Wed, 1 Dec 2021 08:39:45 GMT
Subject: [riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine
 flags register in C2
In-Reply-To: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>
References: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>
Message-ID: <xKSYvTBj3yKUlZK-Hs9lHcd-UJAUVGePhOgzHaMaznQ=.f8b5b787-22a1-4b7d-8313-3da3013561e5@github.com>

On Wed, 1 Dec 2021 07:56:54 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> There are non-allocatable registers t0 and t1 in C2, frequently used as temporary registers for common code snipptes. Meanwhile, C2 use t1 as the flags register, so that many instructs using t1 as a temporary register must declare the data flow effect of t1 which is not part of a match rule. So we can reserve t2 and use it as the machine flags register in C2 instead, to reduce the probability of misuse of t1 without declaring the data flow effect.

This will surely make the code more maintainable. Nice cleanup :-)
No obvious performance impact is witnessed by running specjbb2015 with 't2' used as the dedicate C2 machine flags register.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/21

From fyang at openjdk.java.net  Wed Dec  1 09:10:57 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Wed, 1 Dec 2021 09:10:57 GMT
Subject: [riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine
 flags register in C2
In-Reply-To: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>
References: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>
Message-ID: <1G9odlT-JrX-vnkq0bkmcIh8r71sfhVpLO-bwFA7fKc=.c6a34536-87ef-44ea-9d2f-dcaaabdace88@github.com>

On Wed, 1 Dec 2021 07:56:54 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> There are non-allocatable registers t0 and t1 in C2, frequently used as temporary registers for common code snipptes. Meanwhile, C2 use t1 as the flags register, so that many instructs using t1 as a temporary register must declare the data flow effect of t1 which is not part of a match rule. So we can reserve t2 and use it as the machine flags register in C2 instead, to reduce the probability of misuse of t1 without declaring the data flow effect.

Looks like we missed instructs like: decodeKlass_not_null_with_tmp, string_indexofUU, etc. ? Maybe you can search "rFlagsReg tmp" to find.

-------------

Changes requested by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/21

From yadongwang at openjdk.java.net  Wed Dec  1 09:35:26 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Wed, 1 Dec 2021 09:35:26 GMT
Subject: [riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine
 flags register in C2 [v2]
In-Reply-To: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>
References: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>
Message-ID: <6nmr2Yh797p1XjsyRDfGIqp6WfDbJk-o1dR6mTuxbQk=.d1f741ba-bda9-4228-8cb0-43d0e23b0f32@github.com>

> There are non-allocatable registers t0 and t1 in C2, frequently used as temporary registers for common code snipptes. Meanwhile, C2 use t1 as the flags register, so that many instructs using t1 as a temporary register must declare the data flow effect of t1 which is not part of a match rule. So we can reserve t2 and use it as the machine flags register in C2 instead, to reduce the probability of misuse of t1 without declaring the data flow effect.

Yadong Wang has updated the pull request incrementally with one additional commit since the last revision:

  8278041: riscv: Use t2 as the dedicated machine flags register in C2(2)

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/21/files
  - new: https://git.openjdk.java.net/riscv-port/pull/21/files/b073e926..2e01c8a4

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=21&range=01
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=21&range=00-01

  Stats: 48 lines in 1 file changed: 0 ins; 31 del; 17 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/21.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/21/head:pull/21

PR: https://git.openjdk.java.net/riscv-port/pull/21

From shade at openjdk.java.net  Wed Dec  1 10:02:49 2021
From: shade at openjdk.java.net (Aleksey Shipilev)
Date: Wed, 1 Dec 2021 10:02:49 GMT
Subject: [riscv-port] RFR: 8278033: riscv: Fix MacroAssembler::atomic_incw:
 store condition instruction has wrong operand order
In-Reply-To: <oTHgPnarOVfZgrPw7dB-IU7JRe0j33_uCp9gTQPekWY=.491a0f26-162c-47d9-943b-5621844cf482@github.com>
References: <oTHgPnarOVfZgrPw7dB-IU7JRe0j33_uCp9gTQPekWY=.491a0f26-162c-47d9-943b-5621844cf482@github.com>
Message-ID: <4t4UYxq6s_Soiss6UGq1mbl9PIC548-Qojq87_8loLU=.bf52443c-6ff6-423b-873c-914d04886251@github.com>

On Wed, 1 Dec 2021 02:40:31 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> This is a trivial fix for this typo. This could reproduce before JDK18 by using `-XX:+PrintBiasedLockingStatistics`; however, after the removal of BiasedLocking, this function has no usage now. But we might fix it as well for future usage since it is a quite fundamental function. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/11)

The line above should read "will be zero", right?

Also, shouldn't it be `lr_w(..., acquire)` and `sc_w(..., release)`? I suppose `atomic_incw` has to carry the memory semantics...

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/19

From xlinzheng at openjdk.java.net  Wed Dec  1 10:40:57 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Wed, 1 Dec 2021 10:40:57 GMT
Subject: [riscv-port] RFR: 8278033: riscv: Fix MacroAssembler::atomic_incw:
 store condition instruction has wrong operand order
In-Reply-To: <4t4UYxq6s_Soiss6UGq1mbl9PIC548-Qojq87_8loLU=.bf52443c-6ff6-423b-873c-914d04886251@github.com>
References: <oTHgPnarOVfZgrPw7dB-IU7JRe0j33_uCp9gTQPekWY=.491a0f26-162c-47d9-943b-5621844cf482@github.com>
 <4t4UYxq6s_Soiss6UGq1mbl9PIC548-Qojq87_8loLU=.bf52443c-6ff6-423b-873c-914d04886251@github.com>
Message-ID: <zpIhkbEwuzHxPCKK9VTSkQKB3BbUMZH0CRi4Ydvjtk8=.860987b0-0d2f-4a0d-beb6-5f0675ae2ad5@github.com>

On Wed, 1 Dec 2021 09:59:44 GMT, Aleksey Shipilev <shade at openjdk.org> wrote:

> The line above should read "will be zero", right?
> 
> Also, shouldn't it be `lr_w(..., acquire)` and `sc_w(..., release)`? I suppose `atomic_incw` has to carry the memory semantics...

Thank you for your insight -- though I have no access to the history of this part of code, IMO it may be derived from [the AArch64 counterpart](https://github.com/openjdk/riscv-port/blob/master/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp#L1551-L1567). Seems it only undertakes a simple counting behavior for BiasedLocking before JDK18, like [this code at jdk17-ga](https://github.com/openjdk/jdk/blob/dfacda488bfbe2e11e8d607a6d08527710286982/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp#L487). Currently this function has no usage in both sides of back-ends. I guess this counting behavior may not be so precise? I'm not so good at it and hope I could learn something.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/19

From shade at openjdk.java.net  Wed Dec  1 10:45:50 2021
From: shade at openjdk.java.net (Aleksey Shipilev)
Date: Wed, 1 Dec 2021 10:45:50 GMT
Subject: [riscv-port] RFR: 8278033: riscv: Fix MacroAssembler::atomic_incw:
 store condition instruction has wrong operand order
In-Reply-To: <zpIhkbEwuzHxPCKK9VTSkQKB3BbUMZH0CRi4Ydvjtk8=.860987b0-0d2f-4a0d-beb6-5f0675ae2ad5@github.com>
References: <oTHgPnarOVfZgrPw7dB-IU7JRe0j33_uCp9gTQPekWY=.491a0f26-162c-47d9-943b-5621844cf482@github.com>
 <4t4UYxq6s_Soiss6UGq1mbl9PIC548-Qojq87_8loLU=.bf52443c-6ff6-423b-873c-914d04886251@github.com>
 <zpIhkbEwuzHxPCKK9VTSkQKB3BbUMZH0CRi4Ydvjtk8=.860987b0-0d2f-4a0d-beb6-5f0675ae2ad5@github.com>
Message-ID: <gejuIEuSeG_JvsoEDVXDzbKlOUYNKzxDQo9BWqlrwco=.7a384d62-45e8-473a-bff9-205e27a37757@github.com>

On Wed, 1 Dec 2021 10:37:15 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Thank you for your insight -- though I have no access to the history of this part of code, IMO it may be derived from [the AArch64 counterpart](https://github.com/openjdk/riscv-port/blob/master/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp#L1551-L1567). Seems it only undertakes a simple counting behavior for BiasedLocking before JDK18, like [this code at jdk17-ga](https://github.com/openjdk/jdk/blob/dfacda488bfbe2e11e8d607a6d08527710286982/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp#L487). Currently this function has no usage in both sides of back-ends. I guess this counting behavior may not be so precise? I'm not so good at it and hope I could learn something.

This is not about counting behavior, but rather about the transitive memory ordering from the counters. But I see that AArch64 ` MacroAssembler::atomic_incw` indeed uses `ldxrw`/`stxrw`, which carry no implicit memory ordering. So, this is fine for a single counter in RISC-V too.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/19

From duke at openjdk.java.net  Wed Dec  1 13:14:58 2021
From: duke at openjdk.java.net (kuaiwei)
Date: Wed, 1 Dec 2021 13:14:58 GMT
Subject: [riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine
 flags register in C2 [v2]
In-Reply-To: <6nmr2Yh797p1XjsyRDfGIqp6WfDbJk-o1dR6mTuxbQk=.d1f741ba-bda9-4228-8cb0-43d0e23b0f32@github.com>
References: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>
 <6nmr2Yh797p1XjsyRDfGIqp6WfDbJk-o1dR6mTuxbQk=.d1f741ba-bda9-4228-8cb0-43d0e23b0f32@github.com>
Message-ID: <clf6RXAH1eKel5xuzPlnYNYY-crr8LbfRCJ2d4q21eA=.4d6582c6-827c-4a71-b293-9aa46dd08d16@github.com>

On Wed, 1 Dec 2021 09:35:26 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

>> There are non-allocatable registers t0 and t1 in C2, frequently used as temporary registers for common code snipptes. Meanwhile, C2 use t1 as the flags register, so that many instructs using t1 as a temporary register must declare the data flow effect of t1 which is not part of a match rule. So we can reserve t2 and use it as the machine flags register in C2 instead, to reduce the probability of misuse of t1 without declaring the data flow effect.
>
> Yadong Wang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   8278041: riscv: Use t2 as the dedicated machine flags register in C2(2)

Hi Yadong, it looks cost too much to reserve a dedicated register for control flag. I think in most cases we can use the 2 scratch registers instead. Can you show some complicated cases? We can check if they can be rewrite to avoid the complication.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/21

From fyang at openjdk.java.net  Thu Dec  2 04:04:49 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Thu, 2 Dec 2021 04:04:49 GMT
Subject: [riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine
 flags register in C2 [v2]
In-Reply-To: <clf6RXAH1eKel5xuzPlnYNYY-crr8LbfRCJ2d4q21eA=.4d6582c6-827c-4a71-b293-9aa46dd08d16@github.com>
References: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>
 <6nmr2Yh797p1XjsyRDfGIqp6WfDbJk-o1dR6mTuxbQk=.d1f741ba-bda9-4228-8cb0-43d0e23b0f32@github.com>
 <clf6RXAH1eKel5xuzPlnYNYY-crr8LbfRCJ2d4q21eA=.4d6582c6-827c-4a71-b293-9aa46dd08d16@github.com>
Message-ID: <ckHHdu6sKy28jRIyAOSvFXdhEnr_J1ybEL6g5cHPNas=.be509b04-c1af-4fe7-baf6-e62d258e5af6@github.com>

On Wed, 1 Dec 2021 13:11:44 GMT, kuaiwei <duke at openjdk.java.net> wrote:

> Hi Yadong, it looks cost too much to reserve a dedicated register for control flag. I think in most cases we can use the 2 scratch registers instead. Can you show some complicated cases? We can check if they can be rewrite to avoid the complication.

Well, I think there might be some tradeoff here. 
On the one hand, use the same register 't1' for two different purposes (scratch register & flags registers) at the same time looks rather error prone as mentioned in the PR description. 
On the other hand, use another register 't2' as the dedicated flags register could somehow affect the performance in certain cases even though this is not reflected on the specjbb2015 numbers. 
Personally, I have no obvious bias here. I would like to hear how the other Reviewers would say about this. Maybe @shipilev ?
Thanks.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/21

From yadongwang at openjdk.java.net  Thu Dec  2 13:06:49 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Thu, 2 Dec 2021 13:06:49 GMT
Subject: [riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine
 flags register in C2 [v2]
In-Reply-To: <ckHHdu6sKy28jRIyAOSvFXdhEnr_J1ybEL6g5cHPNas=.be509b04-c1af-4fe7-baf6-e62d258e5af6@github.com>
References: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>
 <6nmr2Yh797p1XjsyRDfGIqp6WfDbJk-o1dR6mTuxbQk=.d1f741ba-bda9-4228-8cb0-43d0e23b0f32@github.com>
 <clf6RXAH1eKel5xuzPlnYNYY-crr8LbfRCJ2d4q21eA=.4d6582c6-827c-4a71-b293-9aa46dd08d16@github.com>
 <ckHHdu6sKy28jRIyAOSvFXdhEnr_J1ybEL6g5cHPNas=.be509b04-c1af-4fe7-baf6-e62d258e5af6@github.com>
Message-ID: <NYCs-AwPo-WWnhgbPvf0m8GnPEpGLAkI2V54RaZx6Sc=.7842f548-1d1e-411c-80ca-2e9c8e926179@github.com>

On Thu, 2 Dec 2021 04:02:02 GMT, Fei Yang <fyang at openjdk.org> wrote:

> > Hi Yadong, it looks cost too much to reserve a dedicated register for control flag. I think in most cases we can use the 2 scratch registers instead. Can you show some complicated cases? We can check if they can be rewrite to avoid the complication.
> 
> Well, I think there might be some tradeoff here. On the one hand, use the same register 't1' for two different purposes (scratch register & flags registers) at the same time looks rather error prone as mentioned in the PR description. On the other hand, use another register 't2' as the dedicated flags register could somehow affect the performance in certain cases even though this is not reflected on the specjbb2015 numbers. Personally, I have no obvious bias here. I would like to hear how the other Reviewers would say about this. Maybe @shipilev ? Thanks.

Agree. it's a tradeoff. There may be more spill/unspills in some scenarios of a high register pressue, but it is more friendly for code scheduling and higher maintainability with less data flow effects. By the way, we found this PR did not affect the performance of SPECjvm2008 on unmatched.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/21

From yadongwang at openjdk.java.net  Thu Dec  2 13:09:52 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Thu, 2 Dec 2021 13:09:52 GMT
Subject: [riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine
 flags register in C2 [v2]
In-Reply-To: <NYCs-AwPo-WWnhgbPvf0m8GnPEpGLAkI2V54RaZx6Sc=.7842f548-1d1e-411c-80ca-2e9c8e926179@github.com>
References: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>
 <6nmr2Yh797p1XjsyRDfGIqp6WfDbJk-o1dR6mTuxbQk=.d1f741ba-bda9-4228-8cb0-43d0e23b0f32@github.com>
 <clf6RXAH1eKel5xuzPlnYNYY-crr8LbfRCJ2d4q21eA=.4d6582c6-827c-4a71-b293-9aa46dd08d16@github.com>
 <ckHHdu6sKy28jRIyAOSvFXdhEnr_J1ybEL6g5cHPNas=.be509b04-c1af-4fe7-baf6-e62d258e5af6@github.com>
 <NYCs-AwPo-WWnhgbPvf0m8GnPEpGLAkI2V54RaZx6Sc=.7842f548-1d1e-411c-80ca-2e9c8e926179@github.com>
Message-ID: <qsA0DW0-TKQtin8MVIzCZ-FanFvpUEBuRHNqB5vUgcg=.b2272c82-c265-4fa6-a286-99efd78c55c5@github.com>

On Thu, 2 Dec 2021 13:04:06 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> Hi Yadong, it looks cost too much to reserve a dedicated register for control flag. I think in most cases we can use the 2 scratch registers instead. Can you show some complicated cases? We can check if they can be rewrite to avoid the complication.

All instructs that remove the rFlagsReg operand are implicitly use t1.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/21

From duke at openjdk.java.net  Fri Dec  3 03:13:35 2021
From: duke at openjdk.java.net (duke)
Date: Fri, 3 Dec 2021 03:13:35 GMT
Subject: git: openjdk/riscv-port: riscv-port: 94 new changesets
Message-ID: <358cb5df-a51d-42a4-9e4d-93a3a90b23a8@openjdk.java.net>

Changeset: 8f9eb620
Author:    Ichiroh Takiguchi <itakiguchi at openjdk.org>
Date:      2021-11-29 00:11:28 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8f9eb620acbc447cf9124b1fe5574a9f02115f45

8274784: jshell: Garbled character was displayed by System.out.println(...) on Japanese Windows

Reviewed-by: naoto

! src/jdk.internal.le/share/classes/jdk/internal/org/jline/terminal/impl/AbstractTerminal.java
! src/jdk.jshell/share/classes/jdk/jshell/execution/RemoteExecutionControl.java

Changeset: c3a7f2f4
Author:    Ludvig Janiuk <ludvig.j.janiuk at oracle.com>
Committer: Tobias Hartmann <thartmann at openjdk.org>
Date:      2021-11-29 06:41:55 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/c3a7f2f4bce9170c1630e01eebd4fcd174b44964

8277382: make c1 BlockMerger use IR::verify only when necessary

Reviewed-by: thartmann, neliasso

! src/hotspot/share/c1/c1_Optimizer.cpp

Changeset: 0c7a4b8a
Author:    Christian Hagedorn <chagedorn at openjdk.org>
Date:      2021-11-29 07:47:28 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/0c7a4b8aa8bb672e87aae7090494719db018b9b1

8277842: IGV: Add jvms property to know where a node came from

Reviewed-by: roland, neliasso, thartmann

! src/hotspot/share/opto/idealGraphPrinter.cpp

Changeset: aed53eea
Author:    Nils Eliasson <neliasso at openjdk.org>
Date:      2021-11-29 08:19:24 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/aed53eea5ea2782c74ea05521462db2ab20b7ebd

8264838: IGV: enhance graph export functionality

Co-authored-by: Roberto Casta?eda Lozano <rcastanedalo at openjdk.org>
Co-authored-by: Nils Eliasson <neliasso at openjdk.org>
Reviewed-by: chagedorn, thartmann

+ src/utils/IdealGraphVisualizer/.java-version
- src/utils/IdealGraphVisualizer/BatikSVGProxy/pom.xml
- src/utils/IdealGraphVisualizer/BatikSVGProxy/src/main/java/com/sun/hotspot/igv/svg/BatikSVG.java
- src/utils/IdealGraphVisualizer/BatikSVGProxy/src/main/java/com/sun/hotspot/igv/svg/package-info.java
- src/utils/IdealGraphVisualizer/BatikSVGProxy/src/main/nbm/manifest.mf
- src/utils/IdealGraphVisualizer/BatikSVGProxy/src/main/resources/com/sun/hotspot/igv/svg/Bundle.properties
! src/utils/IdealGraphVisualizer/View/pom.xml
! src/utils/IdealGraphVisualizer/View/src/main/java/com/sun/hotspot/igv/view/DiagramViewer.java
! src/utils/IdealGraphVisualizer/View/src/main/java/com/sun/hotspot/igv/view/EditorTopComponent.java
! src/utils/IdealGraphVisualizer/View/src/main/java/com/sun/hotspot/igv/view/actions/ExportAction.java
! src/utils/IdealGraphVisualizer/application/pom.xml
! src/utils/IdealGraphVisualizer/pom.xml

Changeset: 9a3a9b13
Author:    Leo Korinth <lkorinth at openjdk.org>
Date:      2021-11-29 09:06:13 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/9a3a9b139178f2645d51a0f12d95a8b424cd5b9d

8277865: G1: Change integer division to floating point division

Reviewed-by: ayang, tschatzl

! src/hotspot/share/gc/g1/g1ConcurrentMark.cpp

Changeset: e3e5908d
Author:    Julia Boes <jboes at openjdk.org>
Date:      2021-11-29 09:22:16 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/e3e5908d0d385ef908ba9752908aaf28b4b3e4f4

8277847: Support toolGuide tag in class-level documentation

Reviewed-by: alanb, jjg

! make/jdk/src/classes/build/tools/taglet/ToolGuide.java

Changeset: 72bacf8d
Author:    Patric Hedlin <phedlin at openjdk.org>
Date:      2021-11-29 10:34:13 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/72bacf8d256071773d8fd9f9c2d0aebb2cb32dea

8276108: Wrong instruction generation in aarch64 backend

Co-authored-by: Nick Gasson <ngasson at openjdk.org>
Reviewed-by: aph, neliasso

! src/hotspot/cpu/aarch64/assembler_aarch64.hpp
! src/hotspot/cpu/aarch64/assembler_aarch64.inline.hpp
! src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp

Changeset: 37de4422
Author:    Andrey Turbanov <turbanoff at gmail.com>
Committer: Erik Gahlin <egahlin at openjdk.org>
Date:      2021-11-29 10:50:43 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/37de442269e8c14e0a112e26a8cbb63e12dec9e7

8275241: Unused ArrayList is created in RequestEngine.addHooks

Reviewed-by: egahlin

! src/jdk.jfr/share/classes/jdk/jfr/internal/RequestEngine.java

Changeset: 2622ab3f
Author:    Thomas Schatzl <tschatzl at openjdk.org>
Date:      2021-11-29 11:58:13 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/2622ab3fe94814fb4f7f22e4015ef1519e546905

8277928: Fix compilation on macosx-aarch64 after 8276108

Reviewed-by: shade, dholmes

! src/hotspot/cpu/aarch64/assembler_aarch64.hpp

Changeset: e5676f8d
Author:    Thomas Schatzl <tschatzl at openjdk.org>
Date:      2021-11-29 12:05:10 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/e5676f8d0b4f9e97497581e848e8b06fb7e11828

8277450: Record number of references into collection set during gc

Reviewed-by: kbarrett, iwalulya

! src/hotspot/share/gc/g1/g1GCPhaseTimes.cpp
! src/hotspot/share/gc/g1/g1GCPhaseTimes.hpp
! src/hotspot/share/gc/g1/g1OopClosures.hpp
! src/hotspot/share/gc/g1/g1OopClosures.inline.hpp
! src/hotspot/share/gc/g1/g1RemSet.cpp
! test/hotspot/jtreg/gc/g1/TestGCLogMessages.java

Changeset: 45e8973a
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-11-29 12:13:51 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/45e8973a22424d76d62cd29f6f934116ceb695fb

8277896: Remove unused BOTConstants member methods

Reviewed-by: kbarrett

! src/hotspot/share/gc/shared/blockOffsetTable.hpp

Changeset: 960bdde7
Author:    Hamlin Li <mli at openjdk.org>
Date:      2021-11-29 12:19:45 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/960bdde7ebc59cefc5c60fc21b8c8267d7c0b631

8277904: G1: Remove G1CardSetArray::max_entries

Reviewed-by: tschatzl

! src/hotspot/share/gc/g1/g1CardSetContainers.hpp

Changeset: 614c6e61
Author:    Volker Simonis <simonis at openjdk.org>
Date:      2021-11-29 12:29:06 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/614c6e61fa3a9f094a311b12e780491c611657e6

8277878: Fix compiler tests after JDK-8275908

Reviewed-by: thartmann, chagedorn

! test/hotspot/jtreg/compiler/exceptions/OptimizeImplicitExceptions.java
! test/hotspot/jtreg/compiler/uncommontrap/Decompile.java

Changeset: ad51d069
Author:    Ivan Walulya <iwalulya at openjdk.org>
Date:      2021-11-29 13:10:06 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ad51d0692534744d04a32959e7e50ee5e87adff5

8277789: G1: G1CardSetConfiguration prefixes num_ and max_ used interchangeably

Reviewed-by: mli, tschatzl

! src/hotspot/share/gc/g1/g1Arguments.cpp
! src/hotspot/share/gc/g1/g1CardSet.cpp
! src/hotspot/share/gc/g1/g1CardSet.hpp
! src/hotspot/share/gc/g1/g1CardSetContainers.inline.hpp
! test/hotspot/gtest/gc/g1/test_g1CardSet.cpp

Changeset: 05ab1767
Author:    Zhengyu Gu <zgu at openjdk.org>
Date:      2021-11-29 14:00:10 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/05ab1767684bee0a3b8c8214c610beafaad058f9

8277797: Remove undefined/unused SharedRuntime::trampoline_size()

Reviewed-by: dholmes, stuefe

! src/hotspot/share/runtime/sharedRuntime.hpp

Changeset: 3d39f09c
Author:    Roman Kennke <rkennke at openjdk.org>
Date:      2021-11-29 16:00:09 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3d39f09c6cdc875b44147b4e84e496b6abf93996

8277654: Shenandoah: Don't produce new memory state in C2 LRB runtime call

Reviewed-by: roland, shade

! src/hotspot/share/gc/shenandoah/c2/shenandoahSupport.cpp
! src/hotspot/share/gc/shenandoah/c2/shenandoahSupport.hpp

Changeset: 825e633e
Author:    Pavel Kharskii <pavel.kharskii at oracle.com>
Committer: Sean Coffey <coffeys at openjdk.org>
Date:      2021-11-29 16:54:47 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/825e633e71ca942fe88c509e7f951ff8903c45cf

8277944: JDK 18 - update GA Release Date

Reviewed-by: coffeys

! make/conf/version-numbers.conf

Changeset: 3a4a94e5
Author:    Jie Fu <jiefu at openjdk.org>
Date:      2021-11-29 23:17:39 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3a4a94e5a830c4e88ac12619b868f3d89aa416a5

8277854: The upper bound of GCCardSizeInBytes should be limited to 512 for 32-bit platforms

Reviewed-by: tschatzl, mli

! src/hotspot/share/gc/shared/gc_globals.hpp

Changeset: 560f9c93
Author:    MeryKitty <anhmdq99 at gmail.com>
Committer: Jie Fu <jiefu at openjdk.org>
Date:      2021-11-29 23:21:04 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/560f9c937233d548ef8db8cd9044fdc6c4cefe41

8277426: Optimize mask reduction operations on x86

Reviewed-by: sviswanathan, jiefu

! src/hotspot/cpu/x86/assembler_x86.cpp
! src/hotspot/cpu/x86/assembler_x86.hpp
! src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp
! src/hotspot/cpu/x86/c2_MacroAssembler_x86.hpp
! src/hotspot/cpu/x86/x86.ad

Changeset: 27299eaa
Author:    Liam Miller-Cushon <cushon at openjdk.org>
Date:      2021-11-30 01:34:52 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/27299eaa98fd2d608a6cecfbf2b1a2a177bd5e9a

8277803: vmTestbase/nsk/jdi/TypeComponent/isSynthetic/issynthetic001 fails with "Synthetic fields not found"

Reviewed-by: dholmes, cjplummer, sspitsyn

! test/hotspot/jtreg/ProblemList.txt
! test/hotspot/jtreg/vmTestbase/nsk/jdi/TypeComponent/isSynthetic/issynthetic001a.java

Changeset: fde6fe79
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-11-30 07:33:46 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/fde6fe7997a889b17af89b3a8fd25456568a1fa6

8277824: Remove empty RefProcSubPhasesWorkerTimeTracker destructor

Co-authored-by: Kim Barrett <kbarrett at openjdk.org>
Reviewed-by: tschatzl, kbarrett

! src/hotspot/share/gc/shared/referenceProcessorPhaseTimes.cpp
! src/hotspot/share/gc/shared/referenceProcessorPhaseTimes.hpp

Changeset: d230feea
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-11-30 07:34:51 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/d230feea55379618a875566b9f9e3b01deb70795

8277931: Parallel: Remove unused PSVirtualSpace::expand_into

Reviewed-by: tschatzl

! src/hotspot/share/gc/parallel/psVirtualspace.cpp
! src/hotspot/share/gc/parallel/psVirtualspace.hpp

Changeset: 3ee26c6a
Author:    David Holmes <dholmes at openjdk.org>
Date:      2021-11-30 08:21:16 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3ee26c6a8152795be281924c26e5def329580352

8267767: Redundant condition check in SafepointSynchronize::thread_not_running

Reviewed-by: hseigel, coleenp, ayang

! src/hotspot/share/runtime/safepoint.cpp

Changeset: ceae380d
Author:    Jie Fu <jiefu at openjdk.org>
Date:      2021-11-30 08:33:00 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ceae380d3a3fcef5678e3073e25eb37ca0a24c46

8277843: [Vector API] scalar2vector generates incorrect type info for mask operations if Op_MaskAll is unavailable

Co-authored-by: Jatin Bhateja <jbhateja at openjdk.org>
Reviewed-by: thartmann, jbhateja

! src/hotspot/share/opto/vectornode.cpp

Changeset: a5f2a58b
Author:    Martin Doerr <mdoerr at openjdk.org>
Date:      2021-11-30 09:20:49 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/a5f2a58ba4ac25f4bd66f1f1f4c036a4f0024229

8277846: Implement fast-path for ASCII-compatible CharsetEncoders on ppc64

Reviewed-by: lucy, mbaesken

! src/hotspot/cpu/ppc/c2_MacroAssembler_ppc.cpp
! src/hotspot/cpu/ppc/c2_MacroAssembler_ppc.hpp
! src/hotspot/cpu/ppc/matcher_ppc.hpp
! src/hotspot/cpu/ppc/ppc.ad

Changeset: fecf906f
Author:    Yi Yang <yyang at openjdk.org>
Date:      2021-11-30 11:50:51 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/fecf906f0af9ddc0e83cb681845009f34555d5dc

8267928: Loop predicate gets inexact loop limit before PhaseIdealLoop::rc_predicate

Reviewed-by: thartmann, chagedorn, kvn

! src/hotspot/share/opto/loopPredicate.cpp

Changeset: 69f56a0e
Author:    Adam Sotona <asotona at openjdk.org>
Date:      2021-11-30 12:56:48 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/69f56a0ea0c2d551b660909deb89f0051540f9d0

8264485: build.tools.depend.Depend.toString(byte[]) creates malformed hex strings

Reviewed-by: jlahoda

! make/jdk/src/classes/build/tools/depend/Depend.java

Changeset: 01cefc94
Author:    Maxim Kartashev <maxim.kartashev at jetbrains.com>
Committer: Magnus Ihse Bursie <ihse at openjdk.org>
Date:      2021-11-30 13:01:17 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/01cefc94c766b87d426cf1dec89a8867454faf0e

8277977: Incorrect references to --enable-reproducible-builds in docs

Reviewed-by: ihse

! doc/building.html
! doc/building.md
! make/autoconf/jdk-options.m4

Changeset: 91508404
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-11-30 13:42:18 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/915084041f32bf6ffe4d12c031ac5e69adcc07f5

8277899: Parallel: Simplify PSVirtualSpace::initialize logic

Reviewed-by: tschatzl, sjohanss

! src/hotspot/share/gc/parallel/objectStartArray.cpp
! src/hotspot/share/gc/parallel/psVirtualspace.cpp
! src/hotspot/share/gc/parallel/psVirtualspace.hpp

Changeset: 98a9f037
Author:    Jorn Vernee <jvernee at openjdk.org>
Date:      2021-11-30 14:34:00 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/98a9f037397d437d2c3221e8522ed8ab397a457a

8277602: Deopt code does not extend the stack enough if the caller is an optimize entry blob

Reviewed-by: dlong, thartmann

! src/hotspot/cpu/x86/universalUpcallHandler_x86_64.cpp
! src/hotspot/share/runtime/deoptimization.cpp
! src/hotspot/share/runtime/frame.hpp
! src/hotspot/share/runtime/vframeArray.cpp
+ test/jdk/java/foreign/upcalldeopt/TestUpcallDeopt.java
= test/jdk/java/foreign/upcalldeopt/libUpcallDeopt.c

Changeset: 21d9ca6c
Author:    Xin Liu <xliu at openjdk.org>
Date:      2021-11-30 18:55:24 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/21d9ca6cd942ac98a3be2577ded8eaf92dac7d46

8274983: C1 optimizes the invocation of private interface methods

Reviewed-by: dlong, iveresov

! src/hotspot/share/c1/c1_GraphBuilder.cpp
+ test/micro/org/openjdk/bench/vm/compiler/InterfacePrivateCalls.java

Changeset: 15a68064
Author:    Kim Barrett <kbarrett at openjdk.org>
Date:      2021-11-30 20:22:35 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/15a680647c4c5df4538e906960c594da79aebf5c

8277434: tests fail with "assert(is_forwarded()) failed: only decode when actually forwarded"

Reviewed-by: ayang, shade, tschatzl

! src/hotspot/share/gc/g1/g1ParScanThreadState.cpp
! src/hotspot/share/gc/g1/g1ParScanThreadState.inline.hpp
! test/hotspot/jtreg/ProblemList.txt

Changeset: 5a4a9bb9
Author:    Daniel D. Daugherty <dcubed at openjdk.org>
Date:      2021-11-30 20:40:10 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/5a4a9bb9d55134deac0e02cf37f31d1dd2223024

8278019: ProblemList java/awt/dnd/BadSerializationTest/BadSerializationTest.java on linux and windows

Reviewed-by: prr

! test/jdk/ProblemList.txt

Changeset: e30e6767
Author:    Petr Portnov <gh at progrm-jarvis.ru>
Committer: Roger Riggs <rriggs at openjdk.org>
Date:      2021-11-30 20:50:13 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/e30e67670981ee905724787c109b7b7fd2b70b42

8277606: String(String) constructor could copy hashIsZero

Reviewed-by: redestad, rriggs

! src/java.base/share/classes/java/lang/String.java

Changeset: 29426469
Author:    Jonathan Gibbons <jjg at openjdk.org>
Date:      2021-11-30 22:07:07 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/2942646957537b2a4b078bc8cb0becab967c21e2

8276683: Malformed Javadoc inline tags in JDK source in com/sun/tools/javac/util/RawDiagnosticFormatter.java

Reviewed-by: darcy, prappo, iris

! src/jdk.compiler/share/classes/com/sun/tools/javac/util/RawDiagnosticFormatter.java

Changeset: f1c20e91
Author:    Naoto Sato <naoto at openjdk.org>
Date:      2021-11-30 22:41:36 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f1c20e91d822c6df4c5da895f2abd6305e00bf8b

8190748: java/text/Format/DateFormat/DateFormatTest.java and NonGregorianFormatTest fail intermittently

Reviewed-by: rriggs, joehw, lancea

! test/jdk/java/text/Format/DateFormat/DateFormatTest.java
! test/jdk/java/text/Format/DateFormat/NonGregorianFormatTest.java

Changeset: 65251f76
Author:    Kim Barrett <kbarrett at openjdk.org>
Date:      2021-11-30 22:43:53 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/65251f76937d1844e2235ce64b42b17f4492d20e

8151594: Move concurrent refinement thread activation logging out of GC pause

Reviewed-by: tschatzl, ayang

! src/hotspot/share/gc/g1/g1ConcurrentRefineThread.cpp

Changeset: dd73e3ce
Author:    Kim Barrett <kbarrett at openjdk.org>
Date:      2021-12-01 00:44:51 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/dd73e3cea238b231b20095de87e94f928700f15a

8277814: ConcurrentRefineThread should report rate when deactivating

Reviewed-by: tschatzl, sjohanss

! src/hotspot/share/gc/g1/g1ConcurrentRefineStats.cpp
! src/hotspot/share/gc/g1/g1ConcurrentRefineStats.hpp
! src/hotspot/share/gc/g1/g1ConcurrentRefineThread.cpp

Changeset: ab867f6c
Author:    Weijun Wang <weijun at openjdk.org>
Date:      2021-12-01 00:48:28 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ab867f6c7c578ae7e65af2989b6836d523a41c5a

8272162: S4U2Self ticket without forwardable flag

Reviewed-by: valeriep

! src/java.base/share/conf/security/java.security
! src/java.security.jgss/share/classes/sun/security/jgss/krb5/Krb5Context.java
! src/java.security.jgss/share/classes/sun/security/jgss/krb5/Krb5InitCredential.java
! src/java.security.jgss/share/classes/sun/security/jgss/krb5/Krb5ProxyCredential.java
! src/java.security.jgss/share/classes/sun/security/krb5/Credentials.java
! src/java.security.jgss/share/classes/sun/security/krb5/KdcComm.java
! src/java.security.jgss/share/classes/sun/security/krb5/KrbAsReq.java
! src/java.security.jgss/share/classes/sun/security/krb5/KrbAsReqBuilder.java
+ src/java.security.jgss/share/classes/sun/security/krb5/KrbKdcReq.java
! src/java.security.jgss/share/classes/sun/security/krb5/KrbTgsRep.java
! src/java.security.jgss/share/classes/sun/security/krb5/KrbTgsReq.java
! src/java.security.jgss/share/classes/sun/security/krb5/internal/CredentialsUtil.java
! src/java.security.jgss/share/classes/sun/security/krb5/internal/KDCReq.java
! src/java.security.jgss/share/classes/sun/security/krb5/internal/ReferralsCache.java
! src/java.security.jgss/share/classes/sun/security/krb5/internal/Ticket.java
! test/jdk/sun/security/krb5/auto/KDC.java
+ test/jdk/sun/security/krb5/auto/S4U2selfNotF.java

Changeset: 7049c13c
Author:    Weijun Wang <weijun at openjdk.org>
Date:      2021-12-01 01:01:57 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/7049c13cf4bf4cdfcd0c8f0fa96bf4c3748ae1e7

8231107: Allow store password to be null when saving a PKCS12 KeyStore

Reviewed-by: mullan

! src/java.base/share/classes/java/security/KeyStore.java
! src/java.base/share/classes/java/security/KeyStoreSpi.java
! src/java.base/share/classes/sun/security/pkcs12/PKCS12KeyStore.java
! test/jdk/sun/security/pkcs12/EmptyPassword.java

Changeset: 0a01baaf
Author:    Jaikiran Pai <jpai at openjdk.org>
Date:      2021-12-01 01:17:07 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/0a01baaf2dd31a0fe2bc8b1327fb072cc3909eeb

8277986: Typo in javadoc of java.util.zip.ZipEntry#setTime

Reviewed-by: alanb, iris, lancea

! src/java.base/share/classes/java/util/zip/ZipEntry.java

Changeset: da2be99c
Author:    Pavel Rappo <prappo at openjdk.org>
Date:      2021-12-01 01:25:17 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/da2be99cfe1121d5a59fa575ea0ac425ad4dbd0f

8277026: Remove blank lines remaining from snippet markup

Reviewed-by: jjg

! src/jdk.javadoc/share/classes/jdk/javadoc/internal/doclets/formats/html/TagletWriterImpl.java
! src/jdk.javadoc/share/classes/jdk/javadoc/internal/doclets/toolkit/taglets/snippet/Parser.java
! src/jdk.javadoc/share/classes/jdk/javadoc/internal/doclets/toolkit/taglets/snippet/Style.java
! src/jdk.javadoc/share/classes/jdk/javadoc/internal/doclets/toolkit/taglets/snippet/StyledText.java
! test/langtools/jdk/javadoc/doclet/testSnippetTag/TestLangProperties.java
! test/langtools/jdk/javadoc/doclet/testSnippetTag/TestSnippetMarkup.java
! test/langtools/jdk/javadoc/doclet/testSnippetTag/TestSnippetTag.java

Changeset: c7331935
Author:    Masanori Yano <myano at openjdk.org>
Committer: Jayathirth D V <jdv at openjdk.org>
Date:      2021-12-01 06:18:44 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/c73319354399596ab2b9aab0a7f62e8fa0ab9365

8262297: ImageIO.write() method will throw IndexOutOfBoundsException

Reviewed-by: serb, jdv

! src/java.desktop/share/classes/com/sun/imageio/plugins/bmp/BMPImageWriter.java
+ test/jdk/javax/imageio/plugins/bmp/BMPBitsPerPixelTest.java

Changeset: 349328c9
Author:    Jie Fu <jiefu at openjdk.org>
Date:      2021-12-01 07:19:44 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/349328c929ccad242a344da69585404e4fea087f

8277777: [Vector API] assert(r->is_XMMRegister()) failed: must be in x86_32.ad

Reviewed-by: thartmann, jbhateja

! src/hotspot/cpu/x86/x86_32.ad

Changeset: 70d5dffb
Author:    Christian Hagedorn <chagedorn at openjdk.org>
Date:      2021-12-01 08:24:59 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/70d5dffb4e7110902b59b56efaef31614916148c

8275326: C2: assert(no_dead_loop) failed: dead loop detected

Reviewed-by: kvn, thartmann

! src/hotspot/share/opto/cfgnode.cpp

Changeset: fde0b95e
Author:    Alan Bateman <alanb at openjdk.org>
Date:      2021-12-01 08:44:51 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/fde0b95ede68c188479852c46df7e28dc4b79594

8277861: Terminally deprecate Thread.stop

Reviewed-by: rriggs, mchung, uschindler, dholmes

! src/java.base/share/classes/java/lang/Thread.java
! src/java.base/share/classes/java/lang/ThreadGroup.java

Changeset: 84aa0a19
Author:    Jayathirth D V <jdv at openjdk.org>
Date:      2021-12-01 10:22:17 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/84aa0a191b085a3d7cb338fd5e67281d0e4b57be

8278047: Few javax/imageio test regressed after JDK-8262297 fix

Reviewed-by: tschatzl

! src/java.desktop/share/classes/com/sun/imageio/plugins/bmp/BMPImageWriter.java
- test/jdk/javax/imageio/plugins/bmp/BMPBitsPerPixelTest.java

Changeset: f505396c
Author:    Julia Boes <jboes at openjdk.org>
Date:      2021-12-01 10:37:09 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f505396cccdd00a284b516dee1e314d1bf285f9e

8277459: Add jwebserver tool

Reviewed-by: michaelm, dfuchs, ihse

+ make/modules/jdk.httpserver/Launcher.gmk
! src/jdk.httpserver/share/classes/com/sun/net/httpserver/SimpleFileServer.java
! src/jdk.httpserver/share/classes/com/sun/net/httpserver/package-info.java
! src/jdk.httpserver/share/classes/module-info.java
+ src/jdk.httpserver/share/classes/sun/net/httpserver/simpleserver/JWebServer.java
! src/jdk.httpserver/share/classes/sun/net/httpserver/simpleserver/Main.java
! src/jdk.httpserver/share/classes/sun/net/httpserver/simpleserver/SimpleFileServerImpl.java
! src/jdk.httpserver/share/classes/sun/net/httpserver/simpleserver/resources/simpleserver.properties
+ src/jdk.httpserver/share/man/jwebserver.1
! test/jdk/com/sun/net/httpserver/simpleserver/CommandLineNegativeTest.java
! test/jdk/com/sun/net/httpserver/simpleserver/CommandLinePortNotSpecifiedTest.java
! test/jdk/com/sun/net/httpserver/simpleserver/CommandLinePositiveTest.java
= test/jdk/com/sun/net/httpserver/simpleserver/jwebserver/CommandLineNegativeTest.java
= test/jdk/com/sun/net/httpserver/simpleserver/jwebserver/CommandLinePortNotSpecifiedTest.java
+ test/jdk/com/sun/net/httpserver/simpleserver/jwebserver/CommandLinePositiveTest.java
! test/jdk/tools/launcher/HelpFlagsTest.java
! test/jdk/tools/launcher/VersionCheck.java

Changeset: 0c29ee50
Author:    Andrey Turbanov <turbanoff at gmail.com>
Committer: Erik Gahlin <egahlin at openjdk.org>
Date:      2021-12-01 11:09:31 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/0c29ee50f07aa003f7cdaaa54f96b5c75b1f04db

8274319: Replace usages of Collections.sort with List.sort call in jdk.jfr

Reviewed-by: egahlin

! src/jdk.jfr/share/classes/jdk/jfr/internal/MetadataReader.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/PlatformRecorder.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/SettingsManager.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/TypeLibrary.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/consumer/RepositoryFiles.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/dcmd/AbstractDCmd.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/dcmd/DCmdCheck.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/tool/EventPrintWriter.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/tool/Metadata.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/tool/Summary.java

Changeset: bc6dce14
Author:    Hamlin Li <mli at openjdk.org>
Date:      2021-12-01 11:26:42 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/bc6dce149efef54b1d6c945c68cd75feb1276f5b

8277736: G1: Allow forced evacuation failure of first N regions in collection set

Reviewed-by: ayang, tschatzl

! src/hotspot/share/gc/g1/g1ParScanThreadState.cpp
! src/hotspot/share/gc/g1/g1ParScanThreadState.hpp
! src/hotspot/share/gc/g1/g1YoungGCEvacFailureInjector.cpp
! src/hotspot/share/gc/g1/g1YoungGCEvacFailureInjector.hpp
! src/hotspot/share/gc/g1/g1YoungGCEvacFailureInjector.inline.hpp
! src/hotspot/share/gc/g1/g1_globals.hpp

Changeset: 8d7958e4
Author:    Aleksey Shipilev <shade at openjdk.org>
Date:      2021-12-01 12:06:07 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8d7958e46969fd59df7bc6dd1cbe31ae63686b05

8277981: String Deduplication table is never cleaned up due to bad dead_factor_for_cleanup

Reviewed-by: zgu, kbarrett, tschatzl

! src/hotspot/share/gc/shared/stringdedup/stringDedupConfig.cpp

Changeset: 37ff7f3b
Author:    KIRIYAMA Takuya <kiriyama.takuya at fujitsu.com>
Committer: Aleksey Shipilev <shade at openjdk.org>
Date:      2021-12-01 12:47:26 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/37ff7f3b66eaa74d62d6a93f2f34ec744db21834

8277866: gc/epsilon/TestMemoryMXBeans.java failed with wrong initial heap size

Reviewed-by: tschatzl, shade

! test/hotspot/jtreg/gc/epsilon/TestMemoryMXBeans.java

Changeset: abaa073b
Author:    Zhengyu Gu <zgu at openjdk.org>
Date:      2021-12-01 13:14:09 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/abaa073bcbdb202658c8a97401ffb098d71e0f16

8277946: NMT: Deprecate and remove VM.native_memory shutdown jcmd command option

Reviewed-by: stuefe, shade, dholmes

! src/hotspot/share/services/nmtDCmd.cpp
! src/hotspot/share/services/nmtDCmd.hpp
! test/hotspot/jtreg/runtime/NMT/JcmdWithNMTDisabled.java
- test/hotspot/jtreg/runtime/NMT/ShutdownTwice.java
- test/hotspot/jtreg/runtime/NMT/SummaryAfterShutdown.java

Changeset: 1e9ed54d
Author:    Ravi Reddy <rreddy at openjdk.org>
Committer: Sean Coffey <coffeys at openjdk.org>
Date:      2021-12-01 15:35:00 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/1e9ed54d362b8c57be5fbbac2de5afbd0f05435f

8193682: Infinite loop in ZipOutputStream.close()

Reviewed-by: lancea, coffeys

! src/java.base/share/classes/java/util/zip/DeflaterOutputStream.java
! src/java.base/share/classes/java/util/zip/GZIPOutputStream.java
! src/java.base/share/classes/java/util/zip/ZipOutputStream.java
+ test/jdk/java/util/zip/CloseDeflaterTest.java

Changeset: 9b3e6720
Author:    Paul Sandoz <psandoz at openjdk.org>
Date:      2021-12-01 16:12:46 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/9b3e67205913daa1960373a4ab33422137082696

8278014: [vectorapi] Remove test run script

Reviewed-by: sviswanathan, jiefu, shade

- test/jdk/jdk/incubator/vector/build-tests.sh
! test/jdk/jdk/incubator/vector/clean.sh
! test/jdk/jdk/incubator/vector/config.sh
! test/jdk/jdk/incubator/vector/gen-tests.sh
- test/jdk/jdk/incubator/vector/run-tests.sh

Changeset: a363b7b9
Author:    Naoto Sato <naoto at openjdk.org>
Date:      2021-12-01 17:14:53 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/a363b7b9217cbb9a7580a87b812da8d5a4215326

8177819: DateTimeFormatterBuilder zone parsing should recognise DST
8277049: ZonedDateTime parse in Fall DST transition fails to retain the correct zonename.

Reviewed-by: joehw, scolebourne

! src/java.base/share/classes/java/time/format/DateTimeFormatter.java
! src/java.base/share/classes/java/time/format/DateTimeFormatterBuilder.java
! src/java.base/share/classes/java/time/format/DateTimeParseContext.java
! src/java.base/share/classes/java/time/format/Parsed.java
! test/jdk/java/time/test/java/time/format/TestZoneTextPrinterParser.java

Changeset: f41e768b
Author:    Andrew Leonard <aleonard at openjdk.org>
Date:      2021-12-01 18:13:16 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f41e768bba2b2ce3b3cc5813ccb1ac4984dcefbd

8277762: Allow configuration of HOTSPOT_BUILD_USER

Reviewed-by: erikj

! make/autoconf/basic.m4
! make/autoconf/jdk-version.m4

Changeset: 0dfb3a70
Author:    Hannes Walln?fer <hannesw at openjdk.org>
Date:      2021-12-01 18:19:26 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/0dfb3a705d2ad0ce4ac0f7dd18fb65d7ae735f16

8268582: javadoc throws NPE with --ignore-source-errors option

Reviewed-by: jjg

! src/jdk.javadoc/share/classes/jdk/javadoc/internal/doclets/toolkit/util/Utils.java
! test/langtools/jdk/javadoc/tool/IgnoreSourceErrors.java

Changeset: 51d6d7a3
Author:    Mikael Vidstedt <mikael at openjdk.org>
Date:      2021-12-01 20:21:38 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/51d6d7a36b760b2b2b77269cc06438108a9931a2

8266839: Enable pandoc on macosx-aarch64 at Oracle

Reviewed-by: erikj

! make/conf/jib-profiles.js

Changeset: 67745fa7
Author:    Hamlin Li <mli at openjdk.org>
Date:      2021-12-02 01:06:45 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/67745fa749e5075b37aeca7db9d446bc287da835

8276299: G1: Unify the wording buffer/node/element in G1SegmentedArrayXxx, G1CardSetXxx and related classes

Reviewed-by: tschatzl, ayang, iwalulya

! src/hotspot/share/gc/g1/g1Arguments.cpp
! src/hotspot/share/gc/g1/g1CardSet.cpp
! src/hotspot/share/gc/g1/g1CardSetContainers.hpp
! src/hotspot/share/gc/g1/g1CardSetContainers.inline.hpp
! src/hotspot/share/gc/g1/g1CardSetMemory.cpp
! src/hotspot/share/gc/g1/g1CardSetMemory.hpp
! src/hotspot/share/gc/g1/g1CardSetMemory.inline.hpp
! src/hotspot/share/gc/g1/g1EvacFailureObjectsSet.cpp
! src/hotspot/share/gc/g1/g1EvacFailureObjectsSet.hpp
! src/hotspot/share/gc/g1/g1RemSetSummary.cpp
! src/hotspot/share/gc/g1/g1SegmentedArray.hpp
! src/hotspot/share/gc/g1/g1SegmentedArray.inline.hpp
! src/hotspot/share/gc/g1/g1SegmentedArrayFreePool.cpp
! src/hotspot/share/gc/g1/g1SegmentedArrayFreePool.hpp

Changeset: 09522db5
Author:    Jaikiran Pai <jpai at openjdk.org>
Date:      2021-12-02 01:29:52 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/09522db5aa9503131381bbb4fe3f2eae829645ce

8277647: [REDO] JDK-8277507 Add jlink.debug system property while launching jpackage tests to help diagonize recent intermittent failures

Reviewed-by: sundar

! test/jdk/tools/jpackage/helpers/jdk/jpackage/test/JPackageCommand.java

Changeset: b226ab99
Author:    Joe Wang <joehw at openjdk.org>
Date:      2021-12-02 02:50:13 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/b226ab99c872e791d3ed9fca015cf92847904c34

8276141: XPathFactory set/getProperty method

Reviewed-by: rriggs, naoto, lancea, iris, alanb

! src/java.xml/share/classes/com/sun/org/apache/xpath/internal/jaxp/XPathFactoryImpl.java
! src/java.xml/share/classes/com/sun/org/apache/xpath/internal/res/XPATHErrorResources.java
! src/java.xml/share/classes/javax/xml/xpath/XPathFactory.java
+ test/jaxp/javax/xml/jaxp/unittest/xpath/XPathFactoryDummyImpl.java
! test/jaxp/javax/xml/jaxp/unittest/xpath/XPathTest.java

Changeset: 8198807b
Author:    Jayathirth D V <jdv at openjdk.org>
Date:      2021-12-02 05:00:48 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8198807b4a811040c7d9f65fb98494fc7d840814

8266435: WBMPImageReader.read() should not truncate the input stream

Reviewed-by: serb

! src/java.desktop/share/classes/com/sun/imageio/plugins/wbmp/WBMPImageReader.java
+ test/jdk/javax/imageio/plugins/wbmp/WBMPStreamTruncateTest.java

Changeset: a093cddd
Author:    Joe Wang <joehw at openjdk.org>
Date:      2021-12-02 06:52:45 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/a093cdddaf5ab88eb84a147e523db5c3e1be54be

8276657: XSLT compiler tries to define a class with empty name

Reviewed-by: naoto

! src/java.xml/share/classes/com/sun/org/apache/xalan/internal/xsltc/compiler/XSLTC.java

Changeset: 088b244e
Author:    Patric Hedlin <phedlin at openjdk.org>
Date:      2021-12-02 09:25:12 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/088b244ec6d9393a1fcd2233fa5b4cf46f9ae0dd

8251216: Implement MD5 intrinsics on AArch64

Co-authored-by: Ludovic Henry <luhenry at openjdk.org>
Reviewed-by: aph, neliasso

! src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp
! src/hotspot/cpu/aarch64/stubRoutines_aarch64.hpp
! src/hotspot/cpu/aarch64/vm_version_aarch64.cpp
! test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java

Changeset: 103da8fa
Author:    Hannes Walln?fer <hannesw at openjdk.org>
Date:      2021-12-02 09:40:24 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/103da8fae12a2aaff1a02a219690ce89fc098641

8274639: Provide a way to disable warnings for cross-modular links

Reviewed-by: jjg

! src/jdk.javadoc/share/classes/jdk/javadoc/internal/doclets/formats/html/resources/standard.properties
! src/jdk.javadoc/share/classes/jdk/javadoc/internal/doclets/toolkit/BaseOptions.java
! src/jdk.javadoc/share/classes/jdk/javadoc/internal/doclets/toolkit/util/Extern.java
! test/langtools/jdk/javadoc/doclet/testLinkOption/TestLinkOptionWithModule.java

Changeset: 84ca14d0
Author:    Markus Gr?nlund <mgronlun at openjdk.org>
Date:      2021-12-02 09:56:39 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/84ca14d0e90fd2c0390a07fc1bcfad0fce14cd3b

8277194: applications/runthese/RunThese30M.java crashes with jfrSymbolTable.cpp:305 assert(_instance != null)

Reviewed-by: shade

! src/hotspot/share/jfr/periodic/jfrFinalizerStatisticsEvent.cpp

Changeset: 16cfbc4f
Author:    Maurizio Cimadamore <mcimadamore at openjdk.org>
Date:      2021-12-02 10:41:36 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/16cfbc4f4c0e979160cc8fb946453fa8afa5d1cc

8278071: typos in MemorySegment::set, MemorySegment::setAtIndex javadoc

Reviewed-by: iris

! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/MemorySegment.java

Changeset: e002bfec
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-12-02 10:45:36 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/e002bfec8cb815b551c9b0f851a8a5b288e8360d

8278049: G1: add precondition to set_remainder_to_point_to_start

Reviewed-by: mli, tschatzl

! src/hotspot/share/gc/g1/g1BlockOffsetTable.cpp

Changeset: ea905bd3
Author:    Maurizio Cimadamore <mcimadamore at openjdk.org>
Date:      2021-12-02 11:22:31 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ea905bd3dad5fc1baad66e714bdd01fa679d2d46

8277924: Small tweaks to foreign function and memory API

Reviewed-by: jvernee, psandoz

! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/FunctionDescriptor.java
! src/jdk.incubator.foreign/share/classes/jdk/internal/foreign/abi/CallingSequenceBuilder.java
! test/jdk/java/foreign/TestFunctionDescriptor.java
! test/jdk/java/foreign/TestIntrinsics.java
! test/jdk/java/foreign/TestUpcall.java
! test/jdk/java/foreign/callarranger/TestSysVCallArranger.java
! test/micro/org/openjdk/bench/jdk/incubator/foreign/Upcalls.java

Changeset: b79554bb
Author:    Hannes Walln?fer <hannesw at openjdk.org>
Date:      2021-12-02 11:33:46 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/b79554bb5cef14590d427543a40efbcc60c66548

8278130: Failure in jdk/javadoc/tool/CheckManPageOptions.java after JDK-8274639

Reviewed-by: prappo

! test/langtools/jdk/javadoc/tool/CheckManPageOptions.java

Changeset: 3d98ec1b
Author:    Jim Laskey <jlaskey at openjdk.org>
Date:      2021-12-02 13:00:14 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3d98ec1b7bc77237177ecfc069c0e9a7e75829bc

8273056: java.util.random does not correctly sample exponential or Gaussian distributions

Co-authored-by: Guy Steele <gls at openjdk.org>
Reviewed-by: bpb, darcy

! src/java.base/share/classes/jdk/internal/util/random/RandomSupport.java

Changeset: 76968979
Author:    Andy Herrick <herrick at openjdk.org>
Date:      2021-12-02 14:08:33 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/7696897932a35708b1632517127c1a3a59919878

8276837: [macos]: Error when signing the additional launcher

Reviewed-by: asemenyuk, almatvee

! src/jdk.jpackage/macosx/classes/jdk/jpackage/internal/MacAppImageBuilder.java
! src/jdk.jpackage/share/classes/jdk/jpackage/internal/IOUtils.java
! test/jdk/tools/jpackage/macosx/SigningAppImageTest.java

Changeset: d2b16c89
Author:    Calvin Cheung <ccheung at openjdk.org>
Date:      2021-12-02 14:39:27 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/d2b16c89855d584a563caa4f725802dc91a83407

8276126: Dump time class transformation causes heap objects of non-boot classes to be archived

Reviewed-by: iklam, minqi

! src/hotspot/share/cds/heapShared.cpp
! src/hotspot/share/cds/heapShared.hpp
! src/hotspot/share/classfile/classLoader.cpp
! src/hotspot/share/classfile/classLoader.hpp
! src/hotspot/share/classfile/classLoaderExt.cpp
! src/hotspot/share/classfile/classLoaderExt.hpp
! src/hotspot/share/classfile/klassFactory.cpp
! test/hotspot/jtreg/TEST.groups
+ test/hotspot/jtreg/runtime/cds/appcds/LambdaWithJavaAgent.java
+ test/hotspot/jtreg/runtime/cds/appcds/test-classes/TransformBootClass.java
+ test/hotspot/jtreg/runtime/cds/appcds/test-classes/TransformBootClass.mf

Changeset: 3889af3f
Author:    Roland Westrelin <roland at openjdk.org>
Date:      2021-12-02 15:09:58 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3889af3f7debc4f8d75f620bb54134d1d11a6c83

8277906: Incorrect type for IV phi of long counted loops after CCP

Reviewed-by: thartmann, chagedorn

! src/hotspot/share/opto/phaseX.cpp
+ test/hotspot/jtreg/compiler/longcountedloops/TestIVPhiTypeIncorrectAfterCCP.java

Changeset: 65960f71
Author:    Jie Fu <jiefu at openjdk.org>
Date:      2021-12-02 15:15:06 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/65960f712ed6d4c4478d74f0842ce78d500d4229

8277753: Long*VectorTests.java fail with "bad AD file" on x86_32 after JDK-8276162

Reviewed-by: kvn, thartmann

! src/hotspot/cpu/x86/x86_32.ad

Changeset: 8d9cb2ef
Author:    Adam Sotona <asotona at openjdk.org>
Date:      2021-12-02 15:29:26 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8d9cb2efe655cc3945b3fe51a5e7d90f48b688e6

8278078: Cannot reference super before supertype constructor has been called

Reviewed-by: mcimadamore

! src/jdk.compiler/share/classes/com/sun/tools/javac/comp/Attr.java
+ test/langtools/tools/javac/8278078/InvalidThisAndSuperInConstructorArgTest.java
+ test/langtools/tools/javac/8278078/InvalidThisAndSuperInConstructorArgTest.out
+ test/langtools/tools/javac/8278078/ValidThisAndSuperInConstructorArgTest.java

Changeset: dc2abc9f
Author:    Andrew Leonard <aleonard at openjdk.org>
Date:      2021-12-02 15:36:43 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/dc2abc9f05c2b7c52aeb242082359c48963f9854

8278080: Add --with-cacerts-src='user cacerts folder' to enable deterministic cacerts generation

Reviewed-by: erikj

! make/autoconf/jdk-options.m4
! make/autoconf/spec.gmk.in
! make/modules/java.base/Gendata.gmk

Changeset: 7c4ef3ab
Author:    Leo Korinth <lkorinth at openjdk.org>
Date:      2021-12-02 15:59:50 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/7c4ef3abaff55b29dddc50f2aea8a04a3214f9fb

8277985: G1: Compare max_parallel_refinement_threads to UINT_MAX

Reviewed-by: kbarrett, tschatzl

! src/hotspot/share/gc/g1/g1Arguments.cpp

Changeset: ad1ff27b
Author:    Lance Andersen <lancea at openjdk.org>
Date:      2021-12-02 16:33:32 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ad1ff27b730773a141d73744e5f5a899bdfbea78

8277422: tools/jar/JarEntryTime.java fails with modified time mismatch

Reviewed-by: joehw, msheppar, naoto

! test/jdk/tools/jar/JarEntryTime.java

Changeset: 8b042d14
Author:    Joe Darcy <darcy at openjdk.org>
Date:      2021-12-02 18:17:32 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8b042d14b78c66b50495d0d8b559ca3f6744d806

8257856: Make ClassFileVersionsTest.java robust to JDK version updates

Reviewed-by: alanb

! test/jdk/java/lang/module/ClassFileVersionsTest.java

Changeset: 8f196a24
Author:    Ao Qi <aoqi at openjdk.org>
Committer: Martin Doerr <mdoerr at openjdk.org>
Date:      2021-12-02 18:57:23 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8f196a2487982a0ae827cdef17243b8c64ba3217

8278037: Clean up PPC32 related code in C1

Reviewed-by: jiefu, stuefe, shade, mdoerr

! src/hotspot/share/c1/c1_LIR.cpp
! src/hotspot/share/c1/c1_LinearScan.cpp
! src/hotspot/share/c1/c1_Runtime1.cpp

Changeset: 4f15be2c
Author:    Liam Miller-Cushon <cushon at openjdk.org>
Date:      2021-12-02 19:17:09 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/4f15be2cd41252d2e5a3f0832f07b98462e9076d

8277965: Enclosing instance optimization affects serialization

Reviewed-by: darcy

! src/jdk.compiler/share/classes/com/sun/tools/javac/comp/Lower.java
! test/langtools/tools/javac/optimizeOuterThis/OptimizeOuterThis.java

Changeset: 669c90e2
Author:    Valerie Peng <valeriep at openjdk.org>
Date:      2021-12-02 19:28:42 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/669c90e23b2397fa9fb4388e8380c95c3b19eb48

8278099: two sun/security/pkcs11/Signature tests failed with AssertionError

Reviewed-by: dcubed

! src/jdk.crypto.cryptoki/share/classes/sun/security/pkcs11/wrapper/CK_MECHANISM.java

Changeset: 30087cc1
Author:    Andrey Turbanov <turbanoff at gmail.com>
Committer: Roger Riggs <rriggs at openjdk.org>
Date:      2021-12-02 19:40:17 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/30087cc1b829e4c2cd77b7c28d077426888160e3

8275342: Change nested classes in java.prefs to static nested classes

Reviewed-by: dfuchs, rriggs

! src/java.prefs/macosx/classes/java/util/prefs/MacOSXPreferencesFile.java
! src/java.prefs/share/classes/java/util/prefs/AbstractPreferences.java
! src/java.prefs/unix/classes/java/util/prefs/FileSystemPreferences.java

Changeset: 73a9654c
Author:    Sergey Tsypanov <sergei.tsypanov at yandex.ru>
Committer: Roger Riggs <rriggs at openjdk.org>
Date:      2021-12-02 20:00:49 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/73a9654c2685e14454a355a16bfe3f6687966f14

8276806: Use Objects.checkFromIndexSize where possible in java.base

Reviewed-by: rriggs, lancea

! src/java.base/share/classes/java/io/ObjectInputStream.java
! src/java.base/share/classes/java/io/ObjectOutputStream.java
! src/java.base/share/classes/java/io/PipedInputStream.java
! src/java.base/share/classes/java/io/PushbackInputStream.java
! src/java.base/share/classes/java/io/SequenceInputStream.java
! src/java.base/share/classes/java/lang/AbstractStringBuilder.java
! src/java.base/share/classes/java/util/zip/DeflaterInputStream.java
! src/java.base/share/classes/java/util/zip/InflaterInputStream.java
! src/java.base/share/classes/java/util/zip/InflaterOutputStream.java
! src/java.base/share/classes/java/util/zip/ZipInputStream.java
! src/java.base/share/classes/java/util/zip/ZipOutputStream.java

Changeset: e0f1fc78
Author:    Scott Gibbons <scott.gibbons at intel.com>
Committer: Sandhya Viswanathan <sviswanathan at openjdk.org>
Date:      2021-12-02 20:06:05 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/e0f1fc783cb492dd1eb18f2d56c57bdc160a410d

8277358: Accelerate CRC32-C

Co-authored-by: Greg Tucker <greg.b.tucker at intel.com>
Co-authored-by: Scott Gibbons <sgibbons at openjdk.org>
Reviewed-by: kvn, sviswanathan, ecaspole

! src/hotspot/cpu/x86/macroAssembler_x86.cpp
! src/hotspot/cpu/x86/stubGenerator_x86_64.cpp
! src/hotspot/cpu/x86/stubRoutines_x86.cpp
! src/hotspot/cpu/x86/stubRoutines_x86.hpp
+ test/micro/org/openjdk/bench/java/util/TestCRC32C.java

Changeset: 652b5f85
Author:    Tim Prinzing <tim at prinzing.net>
Committer: Brent Christian <bchristi at openjdk.org>
Date:      2021-12-02 20:47:29 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/652b5f8546d0453238166f8fcd0cd3d882886bb4

8276674: Malformed Javadoc inline tags in JDK source

Reviewed-by: jjg, rriggs, prappo, bchristi

! src/java.base/share/classes/java/util/stream/AbstractTask.java
! src/java.base/share/classes/java/util/stream/FindOps.java
! src/java.base/share/classes/java/util/stream/Node.java
! src/java.base/share/classes/java/util/stream/Nodes.java
! src/java.base/share/classes/java/util/stream/PipelineHelper.java
! src/jdk.jshell/share/classes/jdk/internal/jshell/tool/Feedback.java
! test/hotspot/jtreg/vmTestbase/nsk/share/ClassFileFinder.java
! test/langtools/tools/javac/classfiles/attributes/lib/TestResult.java

Changeset: 15345e3e
Author:    Brian Burkhalter <bpb at openjdk.org>
Date:      2021-12-02 20:53:13 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/15345e3edcd8beee0d2c3192cfaaf76c7accee1f

8276661: (fs) UserDefinedFileAttributeView no longer works with long path (win)

Reviewed-by: alanb

! src/java.base/windows/classes/sun/nio/fs/WindowsPath.java
! src/java.base/windows/classes/sun/nio/fs/WindowsUserDefinedFileAttributeView.java
! test/jdk/java/nio/file/attribute/UserDefinedFileAttributeView/Basic.java

Changeset: b310f301
Author:    Alexey Ivanov <aivanov at openjdk.org>
Date:      2021-12-02 20:59:46 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/b310f301efd5390408fb56b62cc09eb9a1604413

8277396: [TESTBUG] In DefaultButtonModelCrashTest.java, frame is accessed from main thread

Reviewed-by: serb, psadhukhan

! test/jdk/javax/swing/DefaultButtonModel/DefaultButtonModelCrashTest.java

Changeset: b8ac0d20
Author:    Tim Prinzing <tim.prinzing at oracle.com>
Committer: Lance Andersen <lancea at openjdk.org>
Date:      2021-12-02 21:22:43 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/b8ac0d20ceec26b3a1dd0b9577817fa6320ea9ef

8276681: Additional malformed Javadoc inline tags in JDK source

Reviewed-by: lancea

! src/java.desktop/windows/classes/com/sun/java/swing/plaf/windows/AnimationController.java
! src/java.management/share/classes/javax/management/modelmbean/RequiredModelMBean.java
! src/java.net.http/share/classes/jdk/internal/net/http/ResponseSubscribers.java
! src/java.rmi/share/classes/java/rmi/server/RemoteObject.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/signature/SignatureProperties.java
! src/jdk.compiler/share/classes/com/sun/source/util/Trees.java
! test/jdk/java/awt/Desktop/DesktopEventsExceptions/DesktopEventsExceptions.java
! test/jdk/java/awt/regtesthelpers/process/ProcessCommunicator.java
! test/jdk/java/net/httpclient/reactivestreams-tck/org/reactivestreams/tck/flow/support/PublisherVerificationRules.java

Changeset: c93552c8
Author:    Magnus Ihse Bursie <ihse at openjdk.org>
Date:      2021-12-02 21:31:13 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/c93552c8bbcdabb6219327d67409bf63432f49d8

8277069: [REDO] JDK-8276743 Make openjdk build Zip Archive generation "reproducible"

Co-authored-by: Andrew Leonard <aleonard at openjdk.org>
Co-authored-by: Magnus Ihse Bursie <ihse at openjdk.org>
Reviewed-by: erikj

! make/Main.gmk
! make/ToolsJdk.gmk
! make/common/ZipArchive.gmk
+ make/jdk/src/classes/build/tools/makezipreproducible/MakeZipReproducible.java

Changeset: 19ce33d5
Author:    Chris Plummer <cjplummer at openjdk.org>
Date:      2021-12-02 22:16:55 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/19ce33d5e770dc3fd7a9588e7954bbb499b7a05c

8258512: serviceability/sa/TestJmapCore.java timed out on macOS 10.13.6

Reviewed-by: lmesnik, dcubed

! test/hotspot/jtreg/serviceability/sa/TestJmapCore.java

Changeset: df45709c
Author:    Fei Yang <felix.yang at huawei.com>
Date:      2021-12-02 22:03:34 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/df45709c5649ab216ed604ea1304dd96d118ed86

Merge branch 'master' into riscv-port

! make/hotspot/gensrc/GensrcAdlc.gmk
! src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
! src/hotspot/cpu/riscv/globals_riscv.hpp
! src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
! src/hotspot/cpu/riscv/riscv.ad
= src/hotspot/cpu/riscv/riscv_v.ad
! src/hotspot/share/c1/c1_LIR.cpp
! src/hotspot/share/c1/c1_LinearScan.cpp
! test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java
! make/hotspot/gensrc/GensrcAdlc.gmk
! src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
+ src/hotspot/cpu/riscv/globals_riscv.hpp
+ src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
+ src/hotspot/cpu/riscv/riscv.ad
+ src/hotspot/cpu/riscv/riscv_v.ad
! src/hotspot/share/c1/c1_LIR.cpp
! src/hotspot/share/c1/c1_LinearScan.cpp
! test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java


From yadongwang at openjdk.java.net  Fri Dec  3 08:26:49 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Fri, 3 Dec 2021 08:26:49 GMT
Subject: [riscv-port] RFR: 8278192: riscv: remove unnecessary instruct of
 DecodeNKlass in C2
Message-ID: <YwFv-nLL4D4h7NKd3JlJuQxoNnRR-b6fUXSj-dfB0Sk=.8ef582f6-0f90-40e5-b0fc-24e7a33c6204@github.com>

There are two instructs for DecodeNKlass in C2, and the difference is only that which temporary register operand is used by them, xheapbase, t0 or t1. It's too complicated and the effect is almost invisible. So we just simplify the pattern by using a temporary register from the register allocation.

-------------

Commit messages:
 - 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2

Changes: https://git.openjdk.java.net/riscv-port/pull/22/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=22&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278192
  Stats: 51 lines in 3 files changed: 3 ins; 30 del; 18 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/22.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/22/head:pull/22

PR: https://git.openjdk.java.net/riscv-port/pull/22

From duke at openjdk.java.net  Fri Dec  3 09:00:41 2021
From: duke at openjdk.java.net (kuaiwei)
Date: Fri, 3 Dec 2021 09:00:41 GMT
Subject: [riscv-port] RFR: 8277968: riscv: Detect vector extension with
 vcsr [v2]
In-Reply-To: <-NT5UlFnkXOx4doj-ZlI5cQvVb1aFIkIOVs9H2dFp1E=.2aeb817f-9ba3-4b16-88e8-44ae7d89e214@github.com>
References: <lGp09-9gJ25b4ug7q5loY6mPeiqNj4t4LXiS61VS_ek=.85adc733-85db-46f9-9d9b-544e524cc970@github.com>
 <-NT5UlFnkXOx4doj-ZlI5cQvVb1aFIkIOVs9H2dFp1E=.2aeb817f-9ba3-4b16-88e8-44ae7d89e214@github.com>
Message-ID: <Vx4x2PXst5MiLSaRJiNiY512UHQyeaDq7rELqDAS2wA=.97823ac0-d6ad-416c-ae0d-81433976baff@github.com>

On Tue, 30 Nov 2021 08:04:52 GMT, kuaiwei <duke at openjdk.java.net> wrote:

>> UseRVV could cause crash on D1 board(RISCV-C906).
>> 
>> It seems that though the D1 board is equipped with RVV-0.7.1[1] . In our test, VLENB CSR can return value of 16 on D1 board. So JDK will assume it can support RVV extension and crash in vector instructions when  UseRVV is enabled.  
>> 
>> RVV-0.9 and above[2] introduce a new VCSR CSR register, it will raise SIGILL on D1 board. So we can check it to detect vext support.
>> 
>> 
>> [1] https://github.com/riscv/riscv-v-spec/blob/0a24d0f61b5cd3f1f9265e8c40ab211daa865ede/v-spec.adoc#vector-extension-programmers-model
>> [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-extension-programmers-model
>
> kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.

After offline discussion with Yadong, this patch is pending to wait linux kernel update dts infomation. [1]
So d1 cpu model can be retrieved from /proc/cpuinfo. 

[1] https://github.com/T-head-Semi/linux/blob/linux-5.10.4/arch/riscv/boot/dts/thead/ice.dts#L48

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/18

From duke at openjdk.java.net  Fri Dec  3 09:00:43 2021
From: duke at openjdk.java.net (kuaiwei)
Date: Fri, 3 Dec 2021 09:00:43 GMT
Subject: [riscv-port] Withdrawn: 8277968: riscv: Detect vector extension with
 vcsr
In-Reply-To: <lGp09-9gJ25b4ug7q5loY6mPeiqNj4t4LXiS61VS_ek=.85adc733-85db-46f9-9d9b-544e524cc970@github.com>
References: <lGp09-9gJ25b4ug7q5loY6mPeiqNj4t4LXiS61VS_ek=.85adc733-85db-46f9-9d9b-544e524cc970@github.com>
Message-ID: <bIFDpfiO7j6pEJpFNYyz7b7Kv9lDyvmPtxpPd1lxcuI=.deb8c4fd-0ccc-4157-a855-ec22f562257b@github.com>

On Tue, 30 Nov 2021 07:22:04 GMT, kuaiwei <duke at openjdk.java.net> wrote:

> UseRVV could cause crash on D1 board(RISCV-C906).
> 
> It seems that though the D1 board is equipped with RVV-0.7.1[1] . In our test, VLENB CSR can return value of 16 on D1 board. So JDK will assume it can support RVV extension and crash in vector instructions when  UseRVV is enabled.  
> 
> RVV-0.9 and above[2] introduce a new VCSR CSR register, it will raise SIGILL on D1 board. So we can check it to detect vext support.
> 
> 
> [1] https://github.com/riscv/riscv-v-spec/blob/0a24d0f61b5cd3f1f9265e8c40ab211daa865ede/v-spec.adoc#vector-extension-programmers-model
> [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-extension-programmers-model

This pull request has been closed without being integrated.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/18

From fyang at openjdk.java.net  Fri Dec  3 10:48:42 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Fri, 3 Dec 2021 10:48:42 GMT
Subject: [riscv-port] RFR: 8278192: riscv: remove unnecessary instruct of
 DecodeNKlass in C2
In-Reply-To: <YwFv-nLL4D4h7NKd3JlJuQxoNnRR-b6fUXSj-dfB0Sk=.8ef582f6-0f90-40e5-b0fc-24e7a33c6204@github.com>
References: <YwFv-nLL4D4h7NKd3JlJuQxoNnRR-b6fUXSj-dfB0Sk=.8ef582f6-0f90-40e5-b0fc-24e7a33c6204@github.com>
Message-ID: <gBvNTn58GBevI1x8J22cjsdKlmy1wzH0a5PEyG7mPZE=.04e751db-963b-44db-b91c-9d464e8fba9f@github.com>

On Fri, 3 Dec 2021 08:20:17 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> There are two instructs for DecodeNKlass in C2, and the difference is only that which temporary register operand is used by them, xheapbase, t0 or t1. It's too complicated and the effect is almost invisible. So we just simplify the pattern by using a temporary register from the register allocation.

Changes requested by fyang (Lead).

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 2202:

> 2200:   Label retry_load, nope;
> 2201:   bind(retry_load);
> 2202:   // flush and load exclusive from the memory location

Could you please also fix the comments in MacroAssembler::atomic_incw? Thanks

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/22

From yadongwang at openjdk.java.net  Sun Dec  5 03:13:43 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Sun, 5 Dec 2021 03:13:43 GMT
Subject: [riscv-port] RFR: 8278192: riscv: remove unnecessary instruct of
 DecodeNKlass in C2
In-Reply-To: <gBvNTn58GBevI1x8J22cjsdKlmy1wzH0a5PEyG7mPZE=.04e751db-963b-44db-b91c-9d464e8fba9f@github.com>
References: <YwFv-nLL4D4h7NKd3JlJuQxoNnRR-b6fUXSj-dfB0Sk=.8ef582f6-0f90-40e5-b0fc-24e7a33c6204@github.com>
 <gBvNTn58GBevI1x8J22cjsdKlmy1wzH0a5PEyG7mPZE=.04e751db-963b-44db-b91c-9d464e8fba9f@github.com>
Message-ID: <6w9j5FrDP3GxbDKmr4pKdaW17oLPn17K5bIT-cbC4io=.478200b9-6020-40ab-b67c-9db3a3a8f15e@github.com>

On Fri, 3 Dec 2021 10:45:08 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> There are two instructs for DecodeNKlass in C2, and the difference is only that which temporary register operand is used by them, xheapbase, t0 or t1. It's too complicated and the effect is almost invisible. So we just simplify the pattern by using a temporary register from the register allocation.
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 2202:
> 
>> 2200:   Label retry_load, nope;
>> 2201:   bind(retry_load);
>> 2202:   // flush and load exclusive from the memory location
> 
> Could you please also fix the comments in MacroAssembler::atomic_incw? Thanks

atomic_incw has not been called anywhere, so I'll remove it in the next commit.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/22

From yadongwang at openjdk.java.net  Sun Dec  5 03:26:11 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Sun, 5 Dec 2021 03:26:11 GMT
Subject: [riscv-port] RFR: 8278192: riscv: remove unnecessary instruct of
 DecodeNKlass in C2 [v2]
In-Reply-To: <YwFv-nLL4D4h7NKd3JlJuQxoNnRR-b6fUXSj-dfB0Sk=.8ef582f6-0f90-40e5-b0fc-24e7a33c6204@github.com>
References: <YwFv-nLL4D4h7NKd3JlJuQxoNnRR-b6fUXSj-dfB0Sk=.8ef582f6-0f90-40e5-b0fc-24e7a33c6204@github.com>
Message-ID: <LX3OAaT2zPFgeQ8WDMAC4rba9P5RrjPmpZUtuSx6qXo=.880957c8-91e1-488a-aca5-e9c4da7989a2@github.com>

> There are two instructs for DecodeNKlass in C2, and the difference is only that which temporary register operand is used by them, xheapbase, t0 or t1. It's too complicated and the effect is almost invisible. So we just simplify the pattern by using a temporary register from the register allocation.

Yadong Wang has updated the pull request incrementally with one additional commit since the last revision:

  8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 (2)

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/22/files
  - new: https://git.openjdk.java.net/riscv-port/pull/22/files/d22e7729..cffa3d06

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=22&range=01
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=22&range=00-01

  Stats: 18 lines in 2 files changed: 0 ins; 18 del; 0 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/22.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/22/head:pull/22

PR: https://git.openjdk.java.net/riscv-port/pull/22

From fyang at openjdk.java.net  Mon Dec  6 03:13:44 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Mon, 6 Dec 2021 03:13:44 GMT
Subject: [riscv-port] RFR: 8278192: riscv: remove unnecessary instruct of
 DecodeNKlass in C2 [v2]
In-Reply-To: <LX3OAaT2zPFgeQ8WDMAC4rba9P5RrjPmpZUtuSx6qXo=.880957c8-91e1-488a-aca5-e9c4da7989a2@github.com>
References: <YwFv-nLL4D4h7NKd3JlJuQxoNnRR-b6fUXSj-dfB0Sk=.8ef582f6-0f90-40e5-b0fc-24e7a33c6204@github.com>
 <LX3OAaT2zPFgeQ8WDMAC4rba9P5RrjPmpZUtuSx6qXo=.880957c8-91e1-488a-aca5-e9c4da7989a2@github.com>
Message-ID: <Pg2vcrz9XpQYclUsFACbUnYFWdLqjDzU6PmVEO9x8mM=.175a0987-38b9-4c79-b3ad-aa8d9fe12f50@github.com>

On Sun, 5 Dec 2021 03:26:11 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

>> There are two instructs for DecodeNKlass in C2, and the difference is only that which temporary register operand is used by them, xheapbase, t0 or t1. It's too complicated and the effect is almost invisible. So we just simplify the pattern by using a temporary register from the register allocation.
>
> Yadong Wang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 (2)

Please add the testing carried out for this change in the PR description part. Thanks.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/22

From yzhu at openjdk.java.net  Mon Dec  6 09:58:50 2021
From: yzhu at openjdk.java.net (Yanhong Zhu)
Date: Mon, 6 Dec 2021 09:58:50 GMT
Subject: [riscv-port] RFR: 8276832: riscv: typo in
 LIR_Assembler::check_no_conflict
Message-ID: <FpsGuyZoiObQIYwtBRcNaQzzWw5uvKtblNfPoQFBwg8=.3da7db15-88d0-4875-b913-982a6777fa41@github.com>

This is similar to: 8267625: AARCH64: typo in LIR_Assembler::emit_profile_type.

Difference is that LIR_Assembler::emit_profile_type is refactored and now the typo is in LIR_Assembler::check_no_conflict.

And LIR_Assembler::check_no_conflict is only called by LIR_Assembler::emit_profile_type for now.

-------------

Commit messages:
 - 8276832: riscv: typo in LIR_Assembler::check_no_conflict

Changes: https://git.openjdk.java.net/riscv-port/pull/23/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=23&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8276832
  Stats: 2 lines in 1 file changed: 0 ins; 1 del; 1 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/23.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/23/head:pull/23

PR: https://git.openjdk.java.net/riscv-port/pull/23

From shade at openjdk.java.net  Mon Dec  6 09:58:51 2021
From: shade at openjdk.java.net (Aleksey Shipilev)
Date: Mon, 6 Dec 2021 09:58:51 GMT
Subject: [riscv-port] RFR: 8276832: riscv: typo in
 LIR_Assembler::check_no_conflict
In-Reply-To: <FpsGuyZoiObQIYwtBRcNaQzzWw5uvKtblNfPoQFBwg8=.3da7db15-88d0-4875-b913-982a6777fa41@github.com>
References: <FpsGuyZoiObQIYwtBRcNaQzzWw5uvKtblNfPoQFBwg8=.3da7db15-88d0-4875-b913-982a6777fa41@github.com>
Message-ID: <c2WmmtwYCHCaD-BBvwojIyK_9UXeST3xCbPUiURCjxM=.f135c606-39e9-48ee-a15b-22ccf92bfb3d@github.com>

On Mon, 6 Dec 2021 09:51:14 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

> This is similar to: 8267625: AARCH64: typo in LIR_Assembler::emit_profile_type.
> 
> Difference is that LIR_Assembler::emit_profile_type is refactored and now the typo is in LIR_Assembler::check_no_conflict.
> 
> And LIR_Assembler::check_no_conflict is only called by LIR_Assembler::emit_profile_type for now.

Looks good!

-------------

Marked as reviewed by shade (Reviewer).

PR: https://git.openjdk.java.net/riscv-port/pull/23

From fyang at openjdk.java.net  Tue Dec  7 01:11:42 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Tue, 7 Dec 2021 01:11:42 GMT
Subject: [riscv-port] RFR: 8278192: riscv: remove unnecessary instruct of
 DecodeNKlass in C2 [v2]
In-Reply-To: <LX3OAaT2zPFgeQ8WDMAC4rba9P5RrjPmpZUtuSx6qXo=.880957c8-91e1-488a-aca5-e9c4da7989a2@github.com>
References: <YwFv-nLL4D4h7NKd3JlJuQxoNnRR-b6fUXSj-dfB0Sk=.8ef582f6-0f90-40e5-b0fc-24e7a33c6204@github.com>
 <LX3OAaT2zPFgeQ8WDMAC4rba9P5RrjPmpZUtuSx6qXo=.880957c8-91e1-488a-aca5-e9c4da7989a2@github.com>
Message-ID: <OIqNgG_4ytqg5oI_abf6KQY7S6dDW4mRmeyXzO7AzSo=.ab385dec-3a85-41e7-88d4-986935bf1c00@github.com>

On Sun, 5 Dec 2021 03:26:11 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

>> There are two instructs for DecodeNKlass in C2, and the difference is only that which temporary register operand is used by them, xheapbase, t0 or t1. It's too complicated and the effect is almost invisible. So we just simplify the pattern by using a temporary register from the register allocation.
>> Hotspot and jdk tier1 passed on the unmatched board. And all jtreg tests were tested on qemu without new failures.
>
> Yadong Wang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2 (2)

Looks good.

-------------

Marked as reviewed by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/22

From yzhu at openjdk.java.net  Tue Dec  7 01:21:34 2021
From: yzhu at openjdk.java.net (Yanhong Zhu)
Date: Tue, 7 Dec 2021 01:21:34 GMT
Subject: [riscv-port] RFR: 8276832: riscv: typo in
 LIR_Assembler::check_no_conflict
In-Reply-To: <c2WmmtwYCHCaD-BBvwojIyK_9UXeST3xCbPUiURCjxM=.f135c606-39e9-48ee-a15b-22ccf92bfb3d@github.com>
References: <FpsGuyZoiObQIYwtBRcNaQzzWw5uvKtblNfPoQFBwg8=.3da7db15-88d0-4875-b913-982a6777fa41@github.com>
 <c2WmmtwYCHCaD-BBvwojIyK_9UXeST3xCbPUiURCjxM=.f135c606-39e9-48ee-a15b-22ccf92bfb3d@github.com>
Message-ID: <gkWF5bqY5UhrTGCYpSfRfiYXvtNo4kfrZDHZH4ongT8=.40ada0c8-0328-4337-afc0-13d84c786f93@github.com>

On Mon, 6 Dec 2021 09:53:06 GMT, Aleksey Shipilev <shade at openjdk.org> wrote:

> Looks good!

Thanks for the quick review. Verified with the original testcase. I have pasted the test result in PR description.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/23

From yzhu at openjdk.java.net  Tue Dec  7 01:26:36 2021
From: yzhu at openjdk.java.net (Yanhong Zhu)
Date: Tue, 7 Dec 2021 01:26:36 GMT
Subject: [riscv-port] Integrated: 8276832: riscv: typo in
 LIR_Assembler::check_no_conflict
In-Reply-To: <FpsGuyZoiObQIYwtBRcNaQzzWw5uvKtblNfPoQFBwg8=.3da7db15-88d0-4875-b913-982a6777fa41@github.com>
References: <FpsGuyZoiObQIYwtBRcNaQzzWw5uvKtblNfPoQFBwg8=.3da7db15-88d0-4875-b913-982a6777fa41@github.com>
Message-ID: <zk9WGBD1kGIUnzdXbDVb0N2LmuNPgN8veuqyWV965nk=.a5afebdf-137e-45f0-bc3e-17d57ee3844f@github.com>

On Mon, 6 Dec 2021 09:51:14 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

> This is similar to: 8267625: AARCH64: typo in LIR_Assembler::emit_profile_type.
> 
> Difference is that LIR_Assembler::emit_profile_type is refactored and now the typo is in LIR_Assembler::check_no_conflict.
> 
> And LIR_Assembler::check_no_conflict is only called by LIR_Assembler::emit_profile_type for now.
> 
> The result  of testcase on QEMU?https://bugs.openjdk.java.net/secure/attachment/95368/Test.java??
> Before?
> 
> static Test::test(LTest$A;I)I
>   interpreter_invocation_count:        5376
>   invocation_counter:                  5376
>   backedge_counter:                       0
>   decompile_count:                        0
>   mdo size: 416 bytes
> 
>   ParametersTypeData  0: stack(0) none
> 
> After "ld" -> "sd":
> 
> static Test::test(LTest$A;I)I
>   interpreter_invocation_count:        5376
>   invocation_counter:                  5376
>   backedge_counter:                       0
>   decompile_count:                        0
>   mdo size: 416 bytes
> 
>   ParametersTypeData  0: stack(0) 'Test$A'

This pull request has now been integrated.

Changeset: 997bbe2b
Author:    Yanhong Zhu <yzhu at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/997bbe2b60813a1a5d394b60ba25db9987e5f2fc
Stats:     2 lines in 1 file changed: 0 ins; 1 del; 1 mod

8276832: riscv: typo in LIR_Assembler::check_no_conflict

Reviewed-by: shade

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/23

From yadongwang at openjdk.java.net  Tue Dec  7 01:45:39 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Tue, 7 Dec 2021 01:45:39 GMT
Subject: [riscv-port] Integrated: 8278192: riscv: remove unnecessary instruct
 of DecodeNKlass in C2
In-Reply-To: <YwFv-nLL4D4h7NKd3JlJuQxoNnRR-b6fUXSj-dfB0Sk=.8ef582f6-0f90-40e5-b0fc-24e7a33c6204@github.com>
References: <YwFv-nLL4D4h7NKd3JlJuQxoNnRR-b6fUXSj-dfB0Sk=.8ef582f6-0f90-40e5-b0fc-24e7a33c6204@github.com>
Message-ID: <MjyxL0tJtqo88ZBErB6L9_D_IrESguqUbmRvZtwHvLE=.e3de9c51-880d-48f7-a966-2534c74ab4fd@github.com>

On Fri, 3 Dec 2021 08:20:17 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> There are two instructs for DecodeNKlass in C2, and the difference is only that which temporary register operand is used by them, xheapbase, t0 or t1. It's too complicated and the effect is almost invisible. So we just simplify the pattern by using a temporary register from the register allocation.
> Hotspot and jdk tier1 passed on the unmatched board. And all jtreg tests were tested on qemu without new failures.

This pull request has now been integrated.

Changeset: 63b0d52d
Author:    Yadong Wang <yadongwang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/63b0d52d287cb2a8f3bb1aa3a7eeff89645b9615
Stats:     69 lines in 4 files changed: 3 ins; 48 del; 18 mod

8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2

Reviewed-by: fyang

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/22

From duke at openjdk.java.net  Tue Dec  7 02:23:36 2021
From: duke at openjdk.java.net (duke)
Date: Tue, 7 Dec 2021 02:23:36 GMT
Subject: git: openjdk/riscv-port: riscv-port: 55 new changesets
Message-ID: <8155454a-d379-4ec8-ac6a-b9aa4eb7cf5f@openjdk.java.net>

Changeset: 473ececa
Author:    Jie Fu <jiefu at openjdk.org>
Date:      2021-12-03 06:00:14 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/473ececaf5df8392e76d022d7126770526be31f7

8278174: runtime/cds/appcds/LambdaWithJavaAgent.java fails with release VMs

Reviewed-by: dholmes

! test/hotspot/jtreg/runtime/cds/appcds/LambdaWithJavaAgent.java

Changeset: bef5c7a2
Author:    Aleksey Shipilev <shade at openjdk.org>
Date:      2021-12-03 07:19:48 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/bef5c7a2865e53778e9e476e57c31c0b0f98bcb1

8278116: runtime/modules/LoadUnloadModuleStress.java has duplicate -Xmx

Reviewed-by: dholmes

! test/hotspot/jtreg/runtime/modules/LoadUnloadModuleStress.java

Changeset: 0fbd2713
Author:    Aleksey Shipilev <shade at openjdk.org>
Date:      2021-12-03 07:20:39 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/0fbd2713f1b47c343172fa34be021706c957520e

8278115: gc/stress/gclocker/TestGCLockerWithSerial.java has duplicate -Xmx

Reviewed-by: mli, tschatzl

! test/hotspot/jtreg/gc/stress/gclocker/TestGCLockerWithSerial.java

Changeset: 89070032
Author:    Jan Lahoda <jlahoda at openjdk.org>
Date:      2021-12-03 07:40:34 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/890700320a379c2712fe420017f7b84a8904c0c3

8272234: Pass originating elements from Filer to JavaFileManager

Reviewed-by: jjg

! src/java.compiler/share/classes/javax/tools/ForwardingJavaFileManager.java
! src/java.compiler/share/classes/javax/tools/JavaFileManager.java
! src/jdk.compiler/share/classes/com/sun/tools/javac/api/ClientCodeWrapper.java
! src/jdk.compiler/share/classes/com/sun/tools/javac/main/DelegatingJavaFileManager.java
! src/jdk.compiler/share/classes/com/sun/tools/javac/processing/JavacFiler.java
! test/langtools/tools/javac/api/TestClientCodeWrapper.java
+ test/langtools/tools/javac/processing/filer/TestOriginatingElements.java

Changeset: 45da3aea
Author:    Andrew Leonard <aleonard at openjdk.org>
Date:      2021-12-03 08:28:37 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/45da3aea22fd85f214e661b2c98631cb91ddb55d

8278163: --with-cacerts-src variable resolved after GenerateCacerts recipe setup

Reviewed-by: ihse

! make/modules/java.base/Gendata.gmk

Changeset: d1cad246
Author:    Pavel Rappo <prappo at openjdk.org>
Date:      2021-12-03 09:54:23 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/d1cad2463a3f70d4ff9246d5bbae268bfa6717d7

8278168: Add a few missing words to the specification of Files.mismatch

Reviewed-by: rriggs, bpb, iris, alanb

! src/java.base/share/classes/java/nio/file/Files.java

Changeset: 53df9ffb
Author:    Julia Boes <jboes at openjdk.org>
Date:      2021-12-03 10:18:21 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/53df9ffbca841358eb8bb49837ec4bf43a1a743b

8278154: SimpleFileServer#createFileServer() should specify that the returned server is not started

Reviewed-by: dfuchs

! src/jdk.httpserver/share/classes/com/sun/net/httpserver/SimpleFileServer.java

Changeset: e4774e68
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-12-03 10:57:18 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/e4774e68e3bdb186269e909247bbd1b9f8e4f4be

8277916: Gather non-strong reference count logic in a single place

Reviewed-by: sjohanss, mli

! src/hotspot/share/gc/shared/referenceProcessor.cpp
! src/hotspot/share/gc/shared/referenceProcessorPhaseTimes.cpp
! src/hotspot/share/gc/shared/referenceProcessorPhaseTimes.hpp

Changeset: dda8f26c
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-12-03 10:58:14 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/dda8f26ce0d2b54ef78b74b82e58255aca80576a

8278139: G1: Refactor G1BlockOffsetTablePart::block_at_or_preceding

Reviewed-by: sjohanss, mli

! src/hotspot/share/gc/g1/g1BlockOffsetTable.inline.hpp

Changeset: 18c54b4e
Author:    Andrey Turbanov <turbanoff at gmail.com>
Committer: Alexey Ivanov <aivanov at openjdk.org>
Date:      2021-12-03 13:04:26 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/18c54b4e1ade2ea5531054ed19441d5bff84fcdc

8274640: Cleanup unnecessary null comparison before instanceof check in java.desktop

Reviewed-by: aivanov

! src/java.desktop/macosx/classes/com/apple/laf/AquaBorder.java
! src/java.desktop/macosx/classes/com/apple/laf/AquaButtonBorder.java
! src/java.desktop/macosx/classes/com/apple/laf/AquaComboBoxUI.java
! src/java.desktop/macosx/classes/com/apple/laf/AquaFileChooserUI.java
! src/java.desktop/macosx/classes/com/apple/laf/AquaLookAndFeel.java
! src/java.desktop/macosx/classes/com/apple/laf/AquaRootPaneUI.java
! src/java.desktop/macosx/classes/com/apple/laf/AquaSliderUI.java
! src/java.desktop/macosx/classes/com/apple/laf/AquaTableHeaderUI.java
! src/java.desktop/macosx/classes/com/apple/laf/ScreenMenu.java
! src/java.desktop/macosx/classes/sun/font/CFontManager.java
! src/java.desktop/macosx/classes/sun/lwawt/macosx/CAccessibility.java
! src/java.desktop/macosx/classes/sun/lwawt/macosx/CPlatformWindow.java
! src/java.desktop/macosx/classes/sun/lwawt/macosx/CPrinterJob.java
! src/java.desktop/share/classes/com/sun/imageio/plugins/bmp/BMPImageWriter.java
! src/java.desktop/share/classes/com/sun/imageio/plugins/common/SimpleCMYKColorSpace.java
! src/java.desktop/share/classes/com/sun/imageio/plugins/gif/GIFWritableImageMetadata.java
! src/java.desktop/share/classes/com/sun/imageio/plugins/jpeg/JPEGMetadata.java
! src/java.desktop/share/classes/com/sun/imageio/plugins/tiff/TIFFBaseJPEGCompressor.java
! src/java.desktop/share/classes/com/sun/imageio/plugins/tiff/TIFFImageWriter.java
! src/java.desktop/share/classes/com/sun/java/swing/plaf/motif/MotifFileChooserUI.java
! src/java.desktop/share/classes/com/sun/java/swing/plaf/motif/MotifMenuUI.java
! src/java.desktop/share/classes/com/sun/media/sound/AbstractMidiDevice.java
! src/java.desktop/share/classes/com/sun/media/sound/AudioFloatFormatConverter.java
! src/java.desktop/share/classes/com/sun/media/sound/PortMixer.java
! src/java.desktop/share/classes/com/sun/media/sound/SoftMixingDataLine.java
! src/java.desktop/share/classes/com/sun/media/sound/SoftSynthesizer.java
! src/java.desktop/share/classes/java/awt/AWTEvent.java
! src/java.desktop/share/classes/java/awt/Component.java
! src/java.desktop/share/classes/java/awt/Container.java
! src/java.desktop/share/classes/java/awt/MenuComponent.java
! src/java.desktop/share/classes/java/awt/dnd/DropTarget.java
! src/java.desktop/share/classes/java/awt/image/AreaAveragingScaleFilter.java
! src/java.desktop/share/classes/java/awt/image/ComponentSampleModel.java
! src/java.desktop/share/classes/java/awt/image/MultiPixelPackedSampleModel.java
! src/java.desktop/share/classes/java/awt/image/ReplicateScaleFilter.java
! src/java.desktop/share/classes/java/awt/image/SinglePixelPackedSampleModel.java
! src/java.desktop/share/classes/java/beans/IndexedPropertyDescriptor.java
! src/java.desktop/share/classes/java/beans/PropertyDescriptor.java
! src/java.desktop/share/classes/javax/imageio/ImageTypeSpecifier.java
! src/java.desktop/share/classes/javax/print/DocFlavor.java
! src/java.desktop/share/classes/javax/print/MimeType.java
! src/java.desktop/share/classes/javax/print/attribute/DateTimeSyntax.java
! src/java.desktop/share/classes/javax/print/attribute/HashAttributeSet.java
! src/java.desktop/share/classes/javax/print/attribute/IntegerSyntax.java
! src/java.desktop/share/classes/javax/print/attribute/ResolutionSyntax.java
! src/java.desktop/share/classes/javax/print/attribute/SetOfIntegerSyntax.java
! src/java.desktop/share/classes/javax/print/attribute/Size2DSyntax.java
! src/java.desktop/share/classes/javax/print/attribute/TextSyntax.java
! src/java.desktop/share/classes/javax/print/attribute/URISyntax.java
! src/java.desktop/share/classes/javax/print/attribute/standard/Media.java
! src/java.desktop/share/classes/javax/swing/AbstractAction.java
! src/java.desktop/share/classes/javax/swing/AbstractButton.java
! src/java.desktop/share/classes/javax/swing/DebugGraphics.java
! src/java.desktop/share/classes/javax/swing/JComboBox.java
! src/java.desktop/share/classes/javax/swing/JComponent.java
! src/java.desktop/share/classes/javax/swing/JInternalFrame.java
! src/java.desktop/share/classes/javax/swing/JLabel.java
! src/java.desktop/share/classes/javax/swing/JList.java
! src/java.desktop/share/classes/javax/swing/JMenu.java
! src/java.desktop/share/classes/javax/swing/JMenuBar.java
! src/java.desktop/share/classes/javax/swing/JOptionPane.java
! src/java.desktop/share/classes/javax/swing/JPopupMenu.java
! src/java.desktop/share/classes/javax/swing/JSlider.java
! src/java.desktop/share/classes/javax/swing/JTable.java
! src/java.desktop/share/classes/javax/swing/JTree.java
! src/java.desktop/share/classes/javax/swing/MenuSelectionManager.java
! src/java.desktop/share/classes/javax/swing/RepaintManager.java
! src/java.desktop/share/classes/javax/swing/SpinnerDateModel.java
! src/java.desktop/share/classes/javax/swing/SpinnerNumberModel.java
! src/java.desktop/share/classes/javax/swing/SwingUtilities.java
! src/java.desktop/share/classes/javax/swing/TransferHandler.java
! src/java.desktop/share/classes/javax/swing/event/EventListenerList.java
! src/java.desktop/share/classes/javax/swing/plaf/basic/BasicDesktopPaneUI.java
! src/java.desktop/share/classes/javax/swing/plaf/basic/BasicInternalFrameUI.java
! src/java.desktop/share/classes/javax/swing/plaf/basic/BasicMenuUI.java
! src/java.desktop/share/classes/javax/swing/plaf/basic/BasicOptionPaneUI.java
! src/java.desktop/share/classes/javax/swing/plaf/basic/BasicSpinnerUI.java
! src/java.desktop/share/classes/javax/swing/plaf/basic/BasicSplitPaneUI.java
! src/java.desktop/share/classes/javax/swing/plaf/basic/BasicTableHeaderUI.java
! src/java.desktop/share/classes/javax/swing/plaf/basic/BasicTableUI.java
! src/java.desktop/share/classes/javax/swing/plaf/basic/BasicTextUI.java
! src/java.desktop/share/classes/javax/swing/plaf/basic/BasicToolBarUI.java
! src/java.desktop/share/classes/javax/swing/plaf/basic/BasicTreeUI.java
! src/java.desktop/share/classes/javax/swing/plaf/metal/MetalFileChooserUI.java
! src/java.desktop/share/classes/javax/swing/plaf/synth/SynthTextFieldUI.java
! src/java.desktop/share/classes/javax/swing/plaf/synth/SynthTreeUI.java
! src/java.desktop/share/classes/javax/swing/text/BoxView.java
! src/java.desktop/share/classes/javax/swing/text/DefaultStyledDocument.java
! src/java.desktop/share/classes/javax/swing/text/JTextComponent.java
! src/java.desktop/share/classes/javax/swing/text/html/AccessibleHTML.java
! src/java.desktop/share/classes/javax/swing/text/html/CSS.java
! src/java.desktop/share/classes/javax/swing/text/html/HRuleView.java
! src/java.desktop/share/classes/javax/swing/text/html/HTMLDocument.java
! src/java.desktop/share/classes/javax/swing/text/html/HTMLEditorKit.java
! src/java.desktop/share/classes/javax/swing/text/html/HTMLWriter.java
! src/java.desktop/share/classes/javax/swing/text/html/HiddenTagView.java
! src/java.desktop/share/classes/javax/swing/text/html/Map.java
! src/java.desktop/share/classes/javax/swing/text/html/StyleSheet.java
! src/java.desktop/share/classes/javax/swing/text/rtf/RTFGenerator.java
! src/java.desktop/share/classes/javax/swing/tree/DefaultMutableTreeNode.java
! src/java.desktop/share/classes/javax/swing/tree/DefaultTreeModel.java
! src/java.desktop/share/classes/javax/swing/tree/DefaultTreeSelectionModel.java
! src/java.desktop/share/classes/sun/awt/im/InputContext.java
! src/java.desktop/share/classes/sun/awt/shell/ShellFolder.java
! src/java.desktop/share/classes/sun/font/AttributeValues.java
! src/java.desktop/share/classes/sun/font/FontUtilities.java
! src/java.desktop/share/classes/sun/print/PSStreamPrintService.java
! src/java.desktop/share/classes/sun/print/PathGraphics.java
! src/java.desktop/share/classes/sun/print/PrintJob2D.java
! src/java.desktop/share/classes/sun/print/ServiceDialog.java
! src/java.desktop/share/classes/sun/swing/DefaultLookup.java
! src/java.desktop/share/classes/sun/swing/MenuItemLayoutHelper.java
! src/java.desktop/unix/classes/sun/awt/X11/XComponentPeer.java
! src/java.desktop/unix/classes/sun/awt/X11/XEmbedCanvasPeer.java
! src/java.desktop/unix/classes/sun/awt/X11/XWindow.java
! src/java.desktop/unix/classes/sun/awt/X11/XWindowPeer.java
! src/java.desktop/unix/classes/sun/java2d/xr/XRSurfaceData.java
! src/java.desktop/unix/classes/sun/print/IPPPrintService.java
! src/java.desktop/unix/classes/sun/print/UnixPrintJob.java
! src/java.desktop/windows/classes/com/sun/java/swing/plaf/windows/WindowsFileChooserUI.java
! src/java.desktop/windows/classes/sun/awt/shell/Win32ShellFolder2.java
! src/java.desktop/windows/classes/sun/awt/windows/WPrinterJob.java

Changeset: ba2a8e5a
Author:    Athijegannathan Sundararajan <sundar at openjdk.org>
Date:      2021-12-03 13:20:08 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ba2a8e5a496799451095362279b9dd4b6df20b67

8278205: jlink plugins should dump .class file in debug mode

Reviewed-by: jlaskey

! src/jdk.jlink/share/classes/jdk/tools/jlink/internal/JlinkTask.java
! src/jdk.jlink/share/classes/jdk/tools/jlink/internal/plugins/AbstractPlugin.java
! src/jdk.jlink/share/classes/jdk/tools/jlink/internal/plugins/IncludeLocalesPlugin.java
! src/jdk.jlink/share/classes/jdk/tools/jlink/internal/plugins/StripJavaDebugAttributesPlugin.java
! src/jdk.jlink/share/classes/jdk/tools/jlink/internal/plugins/VersionPropsPlugin.java

Changeset: 3f28a214
Author:    Maurizio Cimadamore <mcimadamore at openjdk.org>
Date:      2021-12-03 13:23:36 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3f28a21414be32375dc0f4b12d349826bacd4810

8278144: Javadoc for MemorySegment::set/MemorySegment::setAtIndex is missing throws tag

Reviewed-by: sundar

! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/MemorySegment.java

Changeset: f7237793
Author:    Denghui Dong <ddong at openjdk.org>
Date:      2021-12-03 13:31:06 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f7237793ffa3a5a804fea49f165c8b9f1935cfac

8278079: C2: expand_dtrace_alloc_probe doesn't take effect in macro.cpp

Reviewed-by: thartmann, kvn, chagedorn

! src/hotspot/share/opto/macro.cpp

Changeset: 53a43427
Author:    Aleksey Shipilev <shade at openjdk.org>
Date:      2021-12-03 15:42:18 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/53a4342783d94cead4d26e5b29d286421b9432c3

8278137: JFR: PrettyWriter uses incorrect year specifier

Reviewed-by: egahlin

! src/jdk.jfr/share/classes/jdk/jfr/internal/tool/PrettyWriter.java

Changeset: 0e7b6bcd
Author:    Aleksey Shipilev <shade at openjdk.org>
Date:      2021-12-03 15:43:51 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/0e7b6bcd8260293c3d39417f04b9b1e4409aa20a

8278141: LIR_OpLoadKlass::_info shadows the field of the same name from LIR_Op

Reviewed-by: thartmann, rkennke

! src/hotspot/share/c1/c1_LIR.hpp

Changeset: 0d938ced
Author:    Brian Burkhalter <bpb at openjdk.org>
Date:      2021-12-03 16:00:27 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/0d938cedcaf55886058b94dc280a8f7181c79fdf

8278172: java/nio/channels/FileChannel/BlockDeviceSize.java should only run on Linux

Reviewed-by: lancea, alanb

! test/jdk/java/nio/channels/FileChannel/BlockDeviceSize.java

Changeset: 0a090926
Author:    Calvin Cheung <ccheung at openjdk.org>
Date:      2021-12-03 16:36:19 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/0a0909263194032ae7d8348484e3638f84090233

8268288: jdk/jfr/api/consumer/streaming/TestOutOfProcessMigration.java fails with "Error: ShouldNotReachHere()"

Reviewed-by: minqi, iklam

! src/hotspot/share/cds/filemap.cpp

Changeset: fbf096ee
Author:    Magnus Ihse Bursie <ihse at openjdk.org>
Date:      2021-12-03 16:56:36 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/fbf096eea46756bdac6f474266caec500c4dc5c5

8251400: Fix incorrect addition of library to test in JDK-8237858

Reviewed-by: dholmes, erikj

! make/common/TestFilesCompilation.gmk
! make/test/JtregNativeJdk.gmk

Changeset: 2e30fa93
Author:    merykitty <anhmdq99 at gmail.com>
Committer: Paul Sandoz <psandoz at openjdk.org>
Date:      2021-12-03 17:07:11 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/2e30fa936dd5fffceb17d338271f5e725c85801c

8278171: [vectorapi] Mask incorrectly computed for zero extending cast

Reviewed-by: psandoz

! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/AbstractVector.java
! test/jdk/jdk/incubator/vector/VectorReshapeTests.java

Changeset: 660f21a4
Author:    Prasanta Sadhukhan <psadhukhan at openjdk.org>
Date:      2021-12-03 17:08:40 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/660f21a418ee4c616d0b91133fd44e74a77d4d53

8278119: ProblemList few headful test failing in macosx12-aarch64 system

Reviewed-by: dcubed

! test/jdk/ProblemList.txt

Changeset: 01cb2b98
Author:    Christian Hagedorn <chagedorn at openjdk.org>
Date:      2021-12-03 17:14:10 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/01cb2b9883d7c9ecdba0ee5bd42124faed4d080c

8277529: SIGSEGV in C2 CompilerThread Node::rematerialize() compiling Packet::readUnsignedTrint

Reviewed-by: thartmann, roland, kvn

! src/hotspot/share/opto/loopPredicate.cpp
! src/hotspot/share/opto/memnode.cpp
+ test/hotspot/jtreg/compiler/loopopts/TestDepBetweenLoopAndPredicate.java

Changeset: 678ac589
Author:    Daniel D. Daugherty <dcubed at openjdk.org>
Date:      2021-12-03 17:22:14 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/678ac589adeba0e9c2ae6d123f05ff20f02082c8

8278240: ProblemList containers/docker/TestJcmd.java on linux-aarch64

Reviewed-by: mseledtsov, tschatzl

! test/hotspot/jtreg/ProblemList.txt

Changeset: 780b8b10
Author:    Joe Darcy <darcy at openjdk.org>
Date:      2021-12-03 18:14:33 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/780b8b1072811208968e4f32f5368eab622fcdcc

8278179: Enable all doclint warnings for build of java.naming

Reviewed-by: iris, erikj

! make/modules/java.naming/Java.gmk

Changeset: 38f525e9
Author:    vamsi-parasa <srinivas.vamsi.parasa at intel.com>
Committer: Sandhya Viswanathan <sviswanathan at openjdk.org>
Date:      2021-12-03 18:17:54 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/38f525e96e767597d16698d4b243b681782acc9f

8275821: Optimize random number generators developed in JDK-8248862 using Math.unsignedMultiplyHigh()

Reviewed-by: psandoz, jlaskey

! src/jdk.random/share/classes/jdk/random/L128X1024MixRandom.java
! src/jdk.random/share/classes/jdk/random/L128X128MixRandom.java
! src/jdk.random/share/classes/jdk/random/L128X256MixRandom.java
+ test/micro/org/openjdk/bench/java/util/RandomGeneratorNext.java

Changeset: a729a70c
Author:    Weijun Wang <weijun at openjdk.org>
Date:      2021-12-03 18:52:17 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/a729a70c0119ed071ff490b0dfd4e3e2cb1a5ae4

8225181: KeyStore should have a getAttributes method

Reviewed-by: mullan

! src/java.base/share/classes/java/security/KeyStore.java
! src/java.base/share/classes/java/security/KeyStoreSpi.java
! src/java.base/share/classes/sun/security/pkcs12/PKCS12KeyStore.java
! src/java.base/share/classes/sun/security/provider/DomainKeyStore.java
! src/java.base/share/classes/sun/security/util/KeyStoreDelegator.java
+ test/jdk/sun/security/pkcs12/GetAttributes.java

Changeset: e1cde19d
Author:    Weijun Wang <weijun at openjdk.org>
Date:      2021-12-03 19:52:18 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/e1cde19dbdbbca365ecfea6d1e2e85a42ed8bde0

8278247: KeyStoreSpi::engineGetAttributes does not throws KeyStoreException

Reviewed-by: mullan

! src/java.base/share/classes/java/security/KeyStoreSpi.java

Changeset: 2b87c2b4
Author:    Jatin Bhateja <jbhateja at openjdk.org>
Date:      2021-12-03 20:21:21 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/2b87c2b429f1c9f0d940795d5f74a54a20c2f5c0

8277793: Support vector F2I and D2L cast operations for X86

Reviewed-by: neliasso, sviswanathan

! src/hotspot/cpu/x86/assembler_x86.cpp
! src/hotspot/cpu/x86/assembler_x86.hpp
! src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp
! src/hotspot/cpu/x86/c2_MacroAssembler_x86.hpp
! src/hotspot/cpu/x86/macroAssembler_x86.cpp
! src/hotspot/cpu/x86/macroAssembler_x86.hpp
! src/hotspot/cpu/x86/x86.ad

Changeset: 24e16ac6
Author:    Sandhya Viswanathan <sviswanathan at openjdk.org>
Date:      2021-12-03 21:06:16 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/24e16ac637095d7dee1d6fe34f996b68eedfa8bc

8277617: Adjust AVX3Threshold for copy/fill stubs

Reviewed-by: jbhateja, dholmes, neliasso, jiefu

! src/hotspot/cpu/x86/macroAssembler_x86.cpp
! src/hotspot/cpu/x86/macroAssembler_x86_arrayCopy_avx3.cpp
! src/hotspot/cpu/x86/stubGenerator_x86_64.cpp
! src/hotspot/cpu/x86/vm_version_x86.cpp
! src/hotspot/cpu/x86/vm_version_x86.hpp

Changeset: 02ee337a
Author:    Joe Darcy <darcy at openjdk.org>
Date:      2021-12-04 02:12:35 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/02ee337ae0d163ae44b1691eb9de12c5608ba178

8278175: Enable all doclint warnings for build of java.desktop

Reviewed-by: erikj, prr

! make/modules/java.desktop/Java.gmk
! src/java.desktop/share/classes/java/awt/BufferCapabilities.java
! src/java.desktop/share/classes/java/awt/Component.java
! src/java.desktop/share/classes/java/awt/event/KeyEvent.java
! src/java.desktop/share/classes/java/beans/beancontext/BeanContextServicesSupport.java
! src/java.desktop/share/classes/java/beans/beancontext/BeanContextSupport.java
! src/java.desktop/share/classes/javax/swing/DefaultListSelectionModel.java
! src/java.desktop/share/classes/javax/swing/JApplet.java
! src/java.desktop/share/classes/javax/swing/JDialog.java
! src/java.desktop/share/classes/javax/swing/JScrollBar.java
! src/java.desktop/share/classes/javax/swing/filechooser/FileSystemView.java
! src/java.desktop/share/classes/javax/swing/plaf/basic/BasicMenuItemUI.java
! src/java.desktop/share/classes/javax/swing/plaf/basic/BasicMenuUI.java
! src/java.desktop/share/classes/javax/swing/plaf/metal/MetalBorders.java
! src/java.desktop/share/classes/javax/swing/text/LayeredHighlighter.java
! src/java.desktop/share/classes/javax/swing/text/html/HTML.java
! src/java.desktop/share/classes/javax/swing/text/html/HTMLEditorKit.java
! src/java.desktop/share/classes/javax/swing/text/html/parser/AttributeList.java
! src/java.desktop/share/classes/javax/swing/text/html/parser/Parser.java
! src/java.desktop/share/classes/javax/swing/undo/UndoableEditSupport.java

Changeset: 9642629d
Author:    Markus Karg <markus at headcrashing.eu>
Committer: Alan Bateman <alanb at openjdk.org>
Date:      2021-12-04 09:27:23 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/9642629d15d9631d8da9a3abdabc40323f3c774b

8276779: (ch) InputStream returned by Channels.newInputStream should have fast path for SelectableChannels

Reviewed-by: lancea, alanb

! src/java.base/share/classes/java/nio/channels/Channels.java
! src/java.base/share/classes/sun/nio/ch/ChannelInputStream.java
! test/jdk/java/nio/channels/Channels/TransferTo.java

Changeset: 267c024e
Author:    Coleen Phillimore <coleenp at openjdk.org>
Date:      2021-12-04 13:05:06 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/267c024eb52acd1611188dd5b1417b877ff3eafd

8265150: AsyncGetCallTrace crashes on ResourceMark

Reviewed-by: dholmes, stuefe, eosterlund, sspitsyn

! src/hotspot/share/oops/method.cpp
! src/hotspot/share/prims/jvmtiEnvBase.cpp

Changeset: 839b6067
Author:    Aleksey Shipilev <shade at openjdk.org>
Date:      2021-12-05 21:38:45 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/839b6067c85cfc260803af9b01dd1e7e7f8388db

8278143: Remove unused "argc" from ConstantPool::copy_bootstrap_arguments_at_impl

Reviewed-by: lfoltan, dholmes

! src/hotspot/share/oops/constantPool.cpp

Changeset: 104aa1f7
Author:    Srikanth Adayapalam <sadayapalam at openjdk.org>
Date:      2021-12-06 06:24:56 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/104aa1f7f9f212318113e304e16e185a6acbec6c

8268575: Annotations not visible on model elements before they are generated

Reviewed-by: mcimadamore

! src/jdk.compiler/share/classes/com/sun/tools/javac/comp/Annotate.java
+ test/langtools/tools/javac/processing/8268575/Processor.java
+ test/langtools/tools/javac/processing/8268575/T8268575.java

Changeset: f180a459
Author:    Aleksey Shipilev <shade at openjdk.org>
Date:      2021-12-06 06:26:50 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f180a4591f52d0af0c030aa85be33c51b06c90ee

8278016: Add compiler tests to tier{2,3}

Reviewed-by: kvn, dholmes

! test/hotspot/jtreg/TEST.groups

Changeset: f39fe5b3
Author:    Tobias Holenstein <tobias.holenstein at oracle.com>
Committer: Tobias Hartmann <thartmann at openjdk.org>
Date:      2021-12-06 08:23:49 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f39fe5b3d629c6d557eb7bab8d1ff81350c616cc

8154011: Make TraceDeoptimization a diagnostic flag

Reviewed-by: kvn, dholmes, thartmann

! src/hotspot/share/runtime/globals.hpp

Changeset: 194cdf4e
Author:    Jan Lahoda <jlahoda at openjdk.org>
Date:      2021-12-06 08:42:26 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/194cdf4e28225133dcdf29cf1bf4e580f3fd9208

8277864: Compilation error thrown while doing a boxing conversion on selector expression

Reviewed-by: jlaskey, vromero

! src/jdk.compiler/share/classes/com/sun/tools/javac/comp/TransPatterns.java
! test/langtools/tools/javac/patterns/Switches.java

Changeset: 8d190dd0
Author:    Ludvig Janiuk <ludvig.j.janiuk at oracle.com>
Committer: Nils Eliasson <neliasso at openjdk.org>
Date:      2021-12-06 08:58:41 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8d190dd003c58aa9ebb403e95a73a128af7e8941

8277496: Remove duplication in c1 Block successor lists

Reviewed-by: neliasso, kvn

! src/hotspot/share/c1/c1_CFGPrinter.cpp
! src/hotspot/share/c1/c1_GraphBuilder.cpp
! src/hotspot/share/c1/c1_IR.cpp
! src/hotspot/share/c1/c1_Instruction.cpp
! src/hotspot/share/c1/c1_Instruction.hpp
! src/hotspot/share/c1/c1_InstructionPrinter.cpp
! src/hotspot/share/c1/c1_LIR.cpp
! src/hotspot/share/c1/c1_Optimizer.cpp

Changeset: d14f06a9
Author:    Markus Gr?nlund <mgronlun at openjdk.org>
Date:      2021-12-06 09:29:28 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/d14f06a9630d2cd2a929d0e44ebe4bb10e20dbd4

8278031: MultiThreadedRefCounter should not use relaxed atomic decrement

Reviewed-by: kbarrett

! src/hotspot/share/jfr/utilities/jfrRefCountPointer.hpp

Changeset: 286a26c3
Author:    Hamlin Li <mli at openjdk.org>
Date:      2021-12-06 11:50:11 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/286a26c36600ed82726f1678194363b2828851dd

8278277: G1: Simplify implementation of G1GCPhaseTimes::record_or_add_time_secs

Reviewed-by: iwalulya, sjohanss, tschatzl

! src/hotspot/share/gc/g1/g1GCPhaseTimes.cpp

Changeset: 6994d809
Author:    Jie Fu <jiefu at openjdk.org>
Date:      2021-12-06 13:44:22 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/6994d809371e80c1e24cd296c48c7f75886577b7

8278291: compiler/uncommontrap/TraceDeoptimizationNoRealloc.java fails with release VMs after JDK-8154011

Reviewed-by: shade, thartmann

! test/hotspot/jtreg/compiler/uncommontrap/TraceDeoptimizationNoRealloc.java

Changeset: a885aab6
Author:    Markus Gr?nlund <mgronlun at openjdk.org>
Date:      2021-12-06 14:36:51 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/a885aab696777c99c8c4c5d9a46afc5fe0a4fe47

8276125: RunThese24H.java SIGSEGV in JfrThreadGroup::thread_group_id

Reviewed-by: egahlin, shade

! src/hotspot/share/jfr/recorder/checkpoint/types/jfrThreadGroup.cpp

Changeset: 7c6f57fc
Author:    Christian Hagedorn <chagedorn at openjdk.org>
Date:      2021-12-06 14:48:03 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/7c6f57fcb1f1fcecf26f7b8046a5a41ca6d9c315

8275610: C2: Object field load floats above its null check resulting in a segfault

Reviewed-by: kvn, roland

! src/hotspot/share/opto/loopopts.cpp
+ test/hotspot/jtreg/compiler/loopopts/TestEliminateNullCheckWithSplitIf.java

Changeset: adf39522
Author:    Vishal Chand <vishalchand2492 at gmail.com>
Committer: Thomas Schatzl <tschatzl at openjdk.org>
Date:      2021-12-06 15:28:20 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/adf39522c178b82dc73e341751b2d9aba984469d

8277372: Add getters for BOT and card table members

Reviewed-by: tschatzl, sjohanss, ayang

! src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.cpp
! src/hotspot/cpu/aarch64/gc/shared/cardTableBarrierSetAssembler_aarch64.cpp
! src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp
! src/hotspot/cpu/arm/gc/g1/g1BarrierSetAssembler_arm.cpp
! src/hotspot/cpu/arm/gc/shared/cardTableBarrierSetAssembler_arm.cpp
! src/hotspot/cpu/ppc/gc/g1/g1BarrierSetAssembler_ppc.cpp
! src/hotspot/cpu/ppc/gc/shared/cardTableBarrierSetAssembler_ppc.cpp
! src/hotspot/cpu/s390/gc/g1/g1BarrierSetAssembler_s390.cpp
! src/hotspot/cpu/s390/gc/shared/cardTableBarrierSetAssembler_s390.cpp
! src/hotspot/cpu/x86/gc/g1/g1BarrierSetAssembler_x86.cpp
! src/hotspot/cpu/x86/gc/shared/cardTableBarrierSetAssembler_x86.cpp
! src/hotspot/share/gc/g1/c2/g1BarrierSetC2.cpp
! src/hotspot/share/gc/g1/g1AllocRegion.cpp
! src/hotspot/share/gc/g1/g1Arguments.cpp
! src/hotspot/share/gc/g1/g1BlockOffsetTable.cpp
! src/hotspot/share/gc/g1/g1BlockOffsetTable.hpp
! src/hotspot/share/gc/g1/g1BlockOffsetTable.inline.hpp
! src/hotspot/share/gc/g1/g1CardCounts.cpp
! src/hotspot/share/gc/g1/g1CardTable.cpp
! src/hotspot/share/gc/g1/g1CardTable.hpp
! src/hotspot/share/gc/g1/g1CardTable.inline.hpp
! src/hotspot/share/gc/g1/g1CollectedHeap.cpp
! src/hotspot/share/gc/g1/g1RemSet.cpp
! src/hotspot/share/gc/g1/heapRegion.cpp
! src/hotspot/share/gc/g1/heapRegionRemSet.cpp
! src/hotspot/share/gc/g1/heapRegionRemSet.inline.hpp
! src/hotspot/share/gc/parallel/objectStartArray.cpp
! src/hotspot/share/gc/parallel/objectStartArray.hpp
! src/hotspot/share/gc/parallel/psOldGen.cpp
! src/hotspot/share/gc/shared/blockOffsetTable.cpp
! src/hotspot/share/gc/shared/blockOffsetTable.hpp
! src/hotspot/share/gc/shared/blockOffsetTable.inline.hpp
! src/hotspot/share/gc/shared/c1/cardTableBarrierSetC1.cpp
! src/hotspot/share/gc/shared/c2/cardTableBarrierSetC2.cpp
! src/hotspot/share/gc/shared/cardTable.cpp
! src/hotspot/share/gc/shared/cardTable.hpp
! src/hotspot/share/gc/shared/vmStructs_gc.hpp
! src/hotspot/share/jvmci/jvmciCompilerToVMInit.cpp
! test/hotspot/gtest/gc/g1/test_freeRegionList.cpp
! test/hotspot/gtest/gc/g1/test_g1CardSetContainers.cpp

Changeset: ab781874
Author:    Jan Lahoda <jlahoda at openjdk.org>
Date:      2021-12-06 15:43:42 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ab781874b27ee4fe1bc6b5fa2cd7997e451e2026

8277105: Inconsistent handling of missing permitted subclasses

Reviewed-by: vromero

! src/jdk.compiler/share/classes/com/sun/tools/javac/comp/Flow.java
! test/langtools/tools/javac/patterns/Exhaustiveness.java
+ test/langtools/tools/javac/sealed/MissingPermittedSubtypes.java

Changeset: 082fdf47
Author:    Prasanta Sadhukhan <psadhukhan at openjdk.org>
Date:      2021-12-06 16:08:28 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/082fdf479367612a7bd795d3becfe9830db4b2d6

8172065: javax/swing/JTree/4908142/bug4908142.java The selected index should be "aad"

Reviewed-by: aivanov

! test/jdk/javax/swing/JTree/4908142/bug4908142.java

Changeset: 587e5409
Author:    Chris Plummer <cjplummer at openjdk.org>
Date:      2021-12-06 16:09:45 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/587e5409c2488cf8c3579a4932c588efc5a02749

8210558: serviceability/sa/TestJhsdbJstackLock.java fails to find '^\s+- waiting to lock <0x[0-9a-f]+> \(a java\.lang\.Class ...'

Reviewed-by: kevinw, sspitsyn

! test/hotspot/jtreg/serviceability/sa/LingeredAppWithLock.java

Changeset: 5045eb53
Author:    Joe Darcy <darcy at openjdk.org>
Date:      2021-12-06 16:56:27 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/5045eb538b3afc6cf646642f1109473597b3004a

8278273: Remove unnecessary exclusion of doclint accessibility checks

Reviewed-by: iris, alanb, ihse

! make/modules/java.base/Java.gmk
! make/modules/java.instrument/Java.gmk
! make/modules/java.logging/Java.gmk
! make/modules/java.management/Java.gmk
! make/modules/java.smartcardio/Java.gmk
! make/modules/java.sql.rowset/Java.gmk
! make/modules/java.xml/Java.gmk

Changeset: 70bad89b
Author:    Artem Semenov <asemenov at openjdk.org>
Date:      2021-12-06 17:39:43 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/70bad89b012eb200ca1e76f384a6e5fb307cf26d

8277497: Last column cell in the JTAble row is read as empty cell

Reviewed-by: ant, kizune, pbansal

! src/java.desktop/share/classes/javax/swing/JLabel.java

Changeset: 2c31a173
Author:    Weijun Wang <weijun at openjdk.org>
Date:      2021-12-06 18:00:54 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/2c31a1735d5b8646ed8984a5475d5c8c9c91c19d

8275082: Update XML Security for Java to 2.3.0

Reviewed-by: mullan

! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/Init.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/algorithms/implementations/IntegrityHmac.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/c14n/implementations/Canonicalizer20010315.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/c14n/implementations/CanonicalizerBase.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/c14n/implementations/CanonicalizerPhysical.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/c14n/implementations/NameSpaceSymbTable.java
- src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/exceptions/XMLSecurityRuntimeException.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/keys/keyresolver/KeyResolver.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/keys/keyresolver/implementations/KeyInfoReferenceResolver.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/resource/config.xml
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/resource/xmlsecurity_en.properties
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/signature/XMLSignatureInput.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/transforms/implementations/TransformC14N.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/transforms/implementations/TransformC14NExclusive.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/transforms/implementations/TransformEnvelopedSignature.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/transforms/implementations/TransformXPath.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/utils/Base64.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/utils/DOMNamespaceContext.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/utils/RFC2253Parser.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/utils/XMLUtils.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/utils/resolver/ResourceResolver.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/utils/resolver/ResourceResolverContext.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/utils/resolver/implementations/ResolverDirectHTTP.java
! src/java.xml.crypto/share/classes/com/sun/org/apache/xml/internal/security/utils/resolver/implementations/ResolverLocalFilesystem.java
! src/java.xml.crypto/share/classes/org/jcp/xml/dsig/internal/dom/ApacheCanonicalizer.java
! src/java.xml.crypto/share/classes/org/jcp/xml/dsig/internal/dom/DOMReference.java
! src/java.xml.crypto/share/classes/org/jcp/xml/dsig/internal/dom/DOMTransform.java
! src/java.xml.crypto/share/classes/org/jcp/xml/dsig/internal/dom/DOMURIDereferencer.java
! src/java.xml.crypto/share/classes/org/jcp/xml/dsig/internal/dom/Policy.java
! src/java.xml.crypto/share/classes/org/jcp/xml/dsig/internal/dom/Utils.java
! src/java.xml.crypto/share/classes/org/jcp/xml/dsig/internal/dom/XMLDSigRI.java
! src/java.xml.crypto/share/legal/santuario.md

Changeset: 239362da
Author:    ANUPAM DEV <anupam.dev at oracle.com>
Committer: Alexey Ivanov <aivanov at openjdk.org>
Date:      2021-12-06 18:46:29 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/239362da51e70b9e968cb488b7c2ec9d91c32837

8247973: Javadoc incorrect for IdentityArrayList, IdentityLinkedList

Reviewed-by: aivanov, prr

! src/java.desktop/share/classes/sun/awt/util/IdentityArrayList.java
! src/java.desktop/share/classes/sun/awt/util/IdentityLinkedList.java

Changeset: ea8d3c92
Author:    Martin Balao <mbalao at openjdk.org>
Date:      2021-12-06 20:31:55 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ea8d3c92c69c393cdbc6c62398f1e9c6adc708d3

8271566: DSA signature length value is not accurate in P11Signature

Reviewed-by: valeriep

! src/jdk.crypto.cryptoki/share/classes/sun/security/pkcs11/P11Key.java
! src/jdk.crypto.cryptoki/share/classes/sun/security/pkcs11/P11Signature.java
+ test/jdk/sun/security/pkcs11/Signature/LargeDSAKey.java

Changeset: 2ff12966
Author:    Ivan ?ipka <isipka at openjdk.org>
Committer: Mark Sheppard <msheppar at openjdk.org>
Date:      2021-12-06 23:34:32 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/2ff12966a345eaa1c16ed73165b3eb273e56f8dd

8277957: Add test group for IPv6 exclusive testing

Reviewed-by: alanb, msheppar

! test/jdk/TEST.groups

Changeset: f148e3e4
Author:    Jonathan Gibbons <jjg at openjdk.org>
Date:      2021-12-07 00:41:11 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f148e3e4623c6d0270a10ba73140e0c37ca5398a

8278318: Create {@index} entries for key LangTools terms

Reviewed-by: darcy

! src/java.compiler/share/classes/module-info.java
! src/jdk.compiler/share/classes/module-info.java

Changeset: 10db0e41
Author:    Weijun Wang <weijun at openjdk.org>
Date:      2021-12-07 01:37:55 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/10db0e41634b62be5c1a931bd54ac4260108670d

8277932: Subject:callAs() not throwing NPE when action is null

Reviewed-by: rriggs

! src/java.base/share/classes/javax/security/auth/Subject.java

Changeset: b46ab9e3
Author:    Fei Yang <felix.yang at huawei.com>
Date:      2021-12-06 21:02:36 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/b46ab9e31d1cac8777a0a0ac61f2fc5c4fa3475f

Merge branch 'master' into riscv-port

! src/hotspot/cpu/riscv/assembler_riscv.hpp
! src/hotspot/cpu/riscv/gc/g1/g1BarrierSetAssembler_riscv.cpp
! src/hotspot/cpu/riscv/gc/shared/cardTableBarrierSetAssembler_riscv.cpp
! src/hotspot/cpu/riscv/javaFrameAnchor_riscv.hpp
! src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
! src/hotspot/cpu/riscv/nativeInst_riscv.hpp
! src/hotspot/share/c1/c1_LIR.cpp
! src/hotspot/share/c1/c1_LIR.hpp
+ src/hotspot/cpu/riscv/assembler_riscv.hpp
+ src/hotspot/cpu/riscv/gc/g1/g1BarrierSetAssembler_riscv.cpp
+ src/hotspot/cpu/riscv/gc/shared/cardTableBarrierSetAssembler_riscv.cpp
+ src/hotspot/cpu/riscv/javaFrameAnchor_riscv.hpp
+ src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
+ src/hotspot/cpu/riscv/nativeInst_riscv.hpp
! src/hotspot/share/c1/c1_LIR.cpp
! src/hotspot/share/c1/c1_LIR.hpp


From xlinzheng at openjdk.java.net  Tue Dec  7 04:55:48 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Tue, 7 Dec 2021 04:55:48 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed instructions
Message-ID: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>

Hi team,

This patch support RISC-V RVC extension. It can introduce:
* 21% code size reduction in template interpreter generated code
* 20%~25% code size reduction in C1 generated code, evaluated by a common SpringBoot program
* 15%~20% code size reduction in C2 generated code, evaluated by a common SpringBoot program

In my observation, the code size footprint could be reduced to nearly a level of the AArch64 back-end. About the performance, there seems a stable ~0.7% performance improvement on SPECjbb2015 on one HiFive Unleashed board, considering the code density increase. I think the performance aspect might be a speculative behavior on different hardware implementations because C910's performance might be better than that, but HiFive Unleashed may be more general.

Things about this patch:
* If an instruction is compressible, then we will implicitly emit a 16-bit compressed instruction instead of the 32-bit instruction in Assembler.
* About the `_nc` postfix of some of Assembler instructions: we know a bunch of places should be reserved for patching, where we cannot change them into compressed instructions. `_nc` is short for `not compressible` - with this, those instructions should keep their origin 4-byte form and remain uncompressed.
* There are things not easy to compress like MachBranchNodes. Please see the comments in the code - currently this patch does not support this. We will support this improvement in patches coming afterward.

The macros after their expansion might be like:

void andr(Register Rd, Register Rs1, Register Rs2) {
  {
    Register src = noreg;
    if (UseCExt && Rs1->is_compressed_valid() && Rs2->is_compressed_valid() &&
        ((src = Rs1, Rs2 == Rd) || (src = Rs2, Rs1 == Rd))) {
      and_c(Rd, Rs2);
      return;
    }
  }
  unsigned insn = 0;
  patch((address)&insn, 6, 0, 0b0110011);
  patch((address)&insn, 14, 12, 0b111);
  patch((address)&insn, 31, 25, 0b0000000);
  patch_reg((address)&insn, 7, Rd);
  patch_reg((address)&insn, 15, Rs1);
  patch_reg((address)&insn, 20, Rs2);
  emit(insn);
};


For further information, please see comments in `assembler_riscv_cext.hpp`.

--

This patch may need some time to acquire a review. I have polished this patch for quite a long time and it might seem stable under a bunch of full-tier tests and some tier1 jdk/hotspot jtreg tests. But I think we might mark it `experimental` at first, though it is turned on by default. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/7), just for reference, might be quite different from the current one.

I am pleased to receive any suggestion.

Thanks,
Xiaolin

-------------

Commit messages:
 - Support RVC: compressed instructions

Changes: https://git.openjdk.java.net/riscv-port/pull/24/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=24&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278322
  Stats: 1891 lines in 29 files changed: 1401 ins; 81 del; 409 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/24.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/24/head:pull/24

PR: https://git.openjdk.java.net/riscv-port/pull/24

From xlinzheng at openjdk.java.net  Tue Dec  7 04:55:48 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Tue, 7 Dec 2021 04:55:48 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
Message-ID: <50glsKkICzbSQfHq7R-ggImggQ8RlzZKK4wd9WFE4Ms=.d646090a-66c7-45f0-aaee-3acd0e86d873@github.com>

On Tue, 7 Dec 2021 04:46:10 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
> 
> This patch support RISC-V RVC extension. It can introduce:
> * 21% code size reduction in template interpreter generated code
> * 20%~25% code size reduction in C1 generated code, evaluated by a common SpringBoot program
> * 15%~20% code size reduction in C2 generated code, evaluated by a common SpringBoot program
> 
> In my observation, the code size footprint could be reduced to nearly a level of the AArch64 back-end. About the performance, there seems a stable ~0.7% performance improvement on SPECjbb2015 on one HiFive Unleashed board, considering the code density increase. I think the performance aspect might be a speculative behavior on different hardware implementations because C910's performance might be better than that, but HiFive Unleashed may be more general.
> 
> Things about this patch:
> * If an instruction is compressible, then we will implicitly emit a 16-bit compressed instruction instead of the 32-bit instruction in Assembler.
> * About the `_nc` postfix of some of Assembler instructions: we know a bunch of places should be reserved for patching, where we cannot change them into compressed instructions. `_nc` is short for `not compressible` - with this, those instructions should keep their origin 4-byte form and remain uncompressed.
> * There are things not easy to compress like MachBranchNodes. Please see the comments in the code - currently this patch does not support this. We will support this improvement in patches coming afterward.
> 
> The macros after their expansion might be like:
> 
> void andr(Register Rd, Register Rs1, Register Rs2) {
>   {
>     Register src = noreg;
>     if (UseCExt && Rs1->is_compressed_valid() && Rs2->is_compressed_valid() &&
>         ((src = Rs1, Rs2 == Rd) || (src = Rs2, Rs1 == Rd))) {
>       and_c(Rd, Rs2);
>       return;
>     }
>   }
>   unsigned insn = 0;
>   patch((address)&insn, 6, 0, 0b0110011);
>   patch((address)&insn, 14, 12, 0b111);
>   patch((address)&insn, 31, 25, 0b0000000);
>   patch_reg((address)&insn, 7, Rd);
>   patch_reg((address)&insn, 15, Rs1);
>   patch_reg((address)&insn, 20, Rs2);
>   emit(insn);
> };
> 
> 
> For further information, please see comments in `assembler_riscv_cext.hpp`.
> 
> --
> 
> This patch may need some time to acquire a review. I have polished this patch for quite a long time and it might seem stable under a bunch of full-tier tests and some tier1 jdk/hotspot jtreg tests. But I think we might mark it `experimental` at first, though it is turned on by default. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/7), just for reference, might be quite different from the current one.
> 
> I am pleased to receive any suggestion.
> 
> Thanks,
> Xiaolin

I would humbly recommend adding my colleague Wei Kuai(kuaiwei.kw at alibaba-inc.com) as a co-author of this patch, especially including facilitating me to troubleshoot [problems](https://github.com/riscv-collab/riscv-openjdk/pull/24) that are not easy to address, out of his insightfulness, and also the support of the compression of MachBranchNodes coming afterward, etc. He has done quite a bunch of contributions to this patch.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24

From yadongwang at openjdk.java.net  Tue Dec  7 08:38:45 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Tue, 7 Dec 2021 08:38:45 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
Message-ID: <Id0jYVmEcM-5eUkU_AqI_nq9v6_VHK5z-I5regDFgCs=.747a91bf-e04c-4b32-8d11-ecd7913fd035@github.com>

On Tue, 7 Dec 2021 04:46:10 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> About the _nc postfix of some of Assembler instructions: we know a bunch of places should be reserved for patching, where we cannot change them into compressed instructions. _nc is short for not compressible - with this, those instructions should keep their origin 4-byte form and remain uncompressed.

Why the compressed instructions can not be patched?

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24

From xlinzheng at openjdk.java.net  Tue Dec  7 09:27:42 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Tue, 7 Dec 2021 09:27:42 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <Id0jYVmEcM-5eUkU_AqI_nq9v6_VHK5z-I5regDFgCs=.747a91bf-e04c-4b32-8d11-ecd7913fd035@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
 <Id0jYVmEcM-5eUkU_AqI_nq9v6_VHK5z-I5regDFgCs=.747a91bf-e04c-4b32-8d11-ecd7913fd035@github.com>
Message-ID: <CFh_IUtVbBOn2iwXKShz_7jLfaHS0OZ3u9zcVz90TZc=.d6458d2e-7809-4493-9df8-8898addd7fb4@github.com>

On Tue, 7 Dec 2021 08:35:53 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> > About the _nc postfix of some of Assembler instructions: we know a bunch of places should be reserved for patching, where we cannot change them into compressed instructions. _nc is short for not compressible - with this, those instructions should keep their origin 4-byte form and remain uncompressed.
> 
> Why the compressed instructions can not be patched?

Thank you for your reviews, yadong. For example, if we need to relocate oops to another place, we may emit a `movptr`, whose length is fixed, including `lui+addi+slli+addi+slli+addi`. For instructions like `addi`s, if we compress them to a 16-byte form, we will face troubles when we want to relocate them to another place since the new address may not be presented by simple `c.addi`s -- because `c.addi` could only present [-32, +31] but `addi` could present [-2048, +2047]. With this respect, it may be a good choice to remain their original forms for the patchable places, though quite conservative.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24

From duke at openjdk.java.net  Tue Dec  7 11:26:53 2021
From: duke at openjdk.java.net (kuaiwei)
Date: Tue, 7 Dec 2021 11:26:53 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around
 calls
Message-ID: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>

It seems zr(x0) is used as stack alignment when saving/restoring registers around calls. But it's unnecessary to ld/st x0 from/to stack. We just need reserve a stack slot in case alignment is required.

-------------

Commit messages:
 - 8278337: riscv: remove unnecessary ld/sd zr around call

Changes: https://git.openjdk.java.net/riscv-port/pull/25/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=25&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278337
  Stats: 19 lines in 2 files changed: 4 ins; 8 del; 7 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/25.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/25/head:pull/25

PR: https://git.openjdk.java.net/riscv-port/pull/25

From fjiang at openjdk.java.net  Tue Dec  7 12:48:31 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Tue, 7 Dec 2021 12:48:31 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr
 around calls
In-Reply-To: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
Message-ID: <KqwS67LHtLTP130isf6iRE3e3T6EIYD9ldTCHBiEz_o=.9893496e-5082-41f1-acd1-48a5ed47931d@github.com>

On Tue, 7 Dec 2021 11:21:00 GMT, kuaiwei <duke at openjdk.java.net> wrote:

> It seems zr(x0) is used as stack alignment when saving/restoring registers around calls. But it's unnecessary to ld/st x0 from/to stack. We just need reserve a stack slot in case alignment is required.

Changes requested by fjiang (Author).

src/hotspot/cpu/riscv/riscv.ad line 1188:

> 1186:     return 12 * NativeInstruction::instruction_size;
> 1187:   }
> 1188: }

`// for real runtime callouts it will be six instructions` should be five instructions now

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/25

From fjiang at openjdk.java.net  Fri Dec 10 01:24:59 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Fri, 10 Dec 2021 01:24:59 GMT
Subject: [riscv-port] RFR: 8278531: riscv: Remove duplicate code
 bitset_to_fregs
Message-ID: <V8NSAQOmj4mS9o9RloTI42a6JBXf8OWzrPXelhH1LiI=.89c2be1b-e780-4411-b29e-45bb3152b65e@github.com>

After JDK-8278337, the definition of `bitset_to_fregs` is just same as `bitset_to_regs`.

Hotspot and jdk tier1 passed on the unmatched board. All tests were tested without new failures.

-------------

Commit messages:
 - 8278531: riscv: Remove duplicate code bitset_to_fregs

Changes: https://git.openjdk.java.net/riscv-port/pull/28/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=28&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278531
  Stats: 17 lines in 2 files changed: 0 ins; 14 del; 3 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/28.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/28/head:pull/28

PR: https://git.openjdk.java.net/riscv-port/pull/28

From fyang at openjdk.java.net  Fri Dec 10 01:35:47 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Fri, 10 Dec 2021 01:35:47 GMT
Subject: [riscv-port] RFR: 8278531: riscv: Remove duplicate code
 bitset_to_fregs
In-Reply-To: <V8NSAQOmj4mS9o9RloTI42a6JBXf8OWzrPXelhH1LiI=.89c2be1b-e780-4411-b29e-45bb3152b65e@github.com>
References: <V8NSAQOmj4mS9o9RloTI42a6JBXf8OWzrPXelhH1LiI=.89c2be1b-e780-4411-b29e-45bb3152b65e@github.com>
Message-ID: <HY8Q5obmqq_PjEej7zSTkfcgbHCX9VhmUhFYnVpaXxY=.5f0bd7de-6b08-4259-ac5a-e2fbc17c4d56@github.com>

On Fri, 10 Dec 2021 01:18:58 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> After [JDK-8278337](https://bugs.openjdk.java.net/browse/JDK-8278337), the definition of `bitset_to_fregs` is just same as `bitset_to_regs`.
> 
> Hotspot and jdk tier1 passed on the unmatched board. All tests were tested without new failures.

Looks good.

-------------

Marked as reviewed by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/28

From duke at openjdk.java.net  Fri Dec 10 01:44:35 2021
From: duke at openjdk.java.net (duke)
Date: Fri, 10 Dec 2021 01:44:35 GMT
Subject: git: openjdk/riscv-port: riscv-port: 46 new changesets
Message-ID: <f503d4fb-13ab-4dad-9050-70e9ff65225e@openjdk.java.net>

Changeset: 10e0318f
Author:    Julia Boes <jboes at openjdk.org>
Date:      2021-12-08 09:16:44 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/10e0318ff7289b248289a70a56adeff3c257de04

8278158: jwebserver should set request timeout

Reviewed-by: dfuchs, michaelm

! src/jdk.httpserver/share/classes/sun/net/httpserver/simpleserver/JWebServer.java
! src/jdk.httpserver/share/classes/sun/net/httpserver/simpleserver/Main.java

Changeset: 54993b13
Author:    Thomas Stuefe <stuefe at openjdk.org>
Date:      2021-12-08 09:18:58 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/54993b13078ceb05736bb0e1d7ed7415c390442e

8278309: [windows] use of uninitialized OSThread::_state

Reviewed-by: dholmes, shade

! src/hotspot/os/windows/os_windows.cpp

Changeset: e5cb84e9
Author:    Markus Gr?nlund <mgronlun at openjdk.org>
Date:      2021-12-08 11:18:24 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/e5cb84e9a1bca321f22d6e3ce13a6026342b4b85

8278336: Use int64_t to represent byte quantities consistently in JfrObjectAllocationSample

Reviewed-by: egahlin

! src/hotspot/share/jfr/support/jfrObjectAllocationSample.cpp

Changeset: fd8cb2da
Author:    Matthias Baesken <mbaesken at openjdk.org>
Date:      2021-12-08 14:03:56 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/fd8cb2dae87e5726e89a1789e5a1ddd461c4400d

8278346: java/nio/file/Files/probeContentType/Basic.java fails on Linux SLES15 machine

Reviewed-by: shade

! test/jdk/java/nio/file/Files/probeContentType/Basic.java

Changeset: 37921e30
Author:    Daniel Fuchs <dfuchs at openjdk.org>
Date:      2021-12-08 15:31:49 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/37921e30803449c06b4d542fdfeed9928cce8a7d

8269258: java/net/httpclient/ManyRequestsLegacy.java failed with connection timeout

Reviewed-by: michaelm

! test/jdk/java/net/httpclient/ManyRequests.java
! test/jdk/java/net/httpclient/ManyRequests2.java
! test/jdk/java/net/httpclient/ManyRequestsLegacy.java

Changeset: e4852c6f
Author:    Calvin Cheung <ccheung at openjdk.org>
Date:      2021-12-08 15:59:37 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/e4852c6f0aa25e7d40c577d507aedc7916ee8d50

8277998: runtime/cds/appcds/loaderConstraints/DynamicLoaderConstraintsTest.java#custom-cl-zgc failed "assert(ZAddress::is_marked(addr)) failed: Should be marked"

Reviewed-by: iklam, minqi

! src/hotspot/share/cds/dynamicArchive.cpp
! src/hotspot/share/cds/lambdaFormInvokers.cpp
! src/hotspot/share/cds/lambdaFormInvokers.hpp
! test/hotspot/jtreg/runtime/cds/appcds/DumpClassListWithLF.java

Changeset: 40d726b8
Author:    Calvin Cheung <ccheung at openjdk.org>
Date:      2021-12-08 16:07:49 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/40d726b8aae7dff4316115b3a25001d502321efe

8278310: Improve logging in CDS DynamicLoaderConstraintsTest.java

Reviewed-by: iklam

! src/hotspot/share/cds/archiveBuilder.hpp
! test/hotspot/jtreg/runtime/cds/appcds/loaderConstraints/DynamicLoaderConstraintsTest.java

Changeset: 79165b73
Author:    Calvin Cheung <ccheung at openjdk.org>
Date:      2021-12-08 16:10:06 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/79165b738d6d1336740631c855960a235b9ecfe4

8278324: Update the --generate-cds-archive jlink plugin usage message

Reviewed-by: alanb

! src/jdk.jlink/share/classes/jdk/tools/jlink/resources/plugins.properties

Changeset: 3e93e0b8
Author:    Yumin Qi <minqi at openjdk.org>
Date:      2021-12-08 16:20:39 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3e93e0b809f2c6cb4a466af92ec678cbc82863e4

8276769: -Xshare:auto should tolerate problems in the CDS archive

Reviewed-by: iklam, ccheung

! src/hotspot/share/cds/filemap.cpp
! src/hotspot/share/include/cds.h
! src/hotspot/share/runtime/arguments.cpp
! src/hotspot/share/runtime/arguments.hpp
! test/hotspot/jtreg/runtime/cds/appcds/SharedArchiveConsistency.java
! test/hotspot/jtreg/runtime/cds/appcds/dynamicArchive/ArchiveConsistency.java
! test/hotspot/jtreg/runtime/cds/appcds/dynamicArchive/DynamicArchiveTestBase.java

Changeset: 8af3b27c
Author:    Roland Westrelin <roland at openjdk.org>
Date:      2021-12-08 16:39:24 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8af3b27ce98bcb9cf0c155c98d6b9a9bc159aafe

8277850: C2: optimize mask checks in counted loops

Reviewed-by: kvn, thartmann

! src/hotspot/share/opto/mulnode.cpp
! src/hotspot/share/opto/mulnode.hpp
+ test/hotspot/jtreg/compiler/c2/irTests/TestShiftAndMask.java
! test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java

Changeset: 24781588
Author:    Brian Burkhalter <bpb at openjdk.org>
Date:      2021-12-08 17:11:14 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/2478158815a9ae0466542e27562bff046d760d3e

8277361: java/nio/channels/Channels/ReadXBytes.java fails with OOM error

Reviewed-by: alanb, lancea

! test/jdk/java/nio/channels/Channels/ReadXBytes.java

Changeset: 9b747491
Author:    Valerie Peng <valeriep at openjdk.org>
Date:      2021-12-08 17:44:10 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/9b747491de01fd011b09668a67113e80c2b7c708

8276660: Scalability bottleneck in java.security.Provider.getService()

Reviewed-by: weijun

! src/java.base/share/classes/java/security/Provider.java

Changeset: 83454530
Author:    Alexey Ushakov <avu at openjdk.org>
Date:      2021-12-08 17:48:53 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/83454530ea538c80e2f1205cd8d2f9732503b592

8272392: Lanai: SwingSet2. Black background on expanding tree node

Reviewed-by: aghaisas, jdv

! src/java.desktop/macosx/native/libawt_lwawt/java2d/metal/EncoderManager.m
! src/java.desktop/macosx/native/libawt_lwawt/java2d/metal/MTLBlitLoops.m
! src/java.desktop/macosx/native/libawt_lwawt/java2d/metal/MTLClip.m
! src/java.desktop/macosx/native/libawt_lwawt/java2d/metal/MTLPaints.m
! src/java.desktop/macosx/native/libawt_lwawt/java2d/metal/MTLPipelineStatesStorage.m
! src/java.desktop/macosx/native/libawt_lwawt/java2d/metal/RenderOptions.h
! src/java.desktop/macosx/native/libawt_lwawt/java2d/metal/common.h

Changeset: 92aa75b7
Author:    Aleksey Shipilev <shade at openjdk.org>
Date:      2021-12-08 17:52:03 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/92aa75b72185c681757e6520d6fdc1ae4161d0c5

8274903: Zero: Support AsyncGetCallTrace

Reviewed-by: sspitsyn, aph

! src/hotspot/cpu/zero/frame_zero.cpp
! src/hotspot/os_cpu/linux_zero/thread_linux_zero.cpp
! src/hotspot/os_cpu/linux_zero/thread_linux_zero.hpp
! src/hotspot/share/prims/forte.cpp

Changeset: ba86dd4a
Author:    Daniel D. Daugherty <dcubed at openjdk.org>
Date:      2021-12-08 18:02:34 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ba86dd4aaf597a0f0832085b50fa00498f053a6a

8278445: ProblemList tools/jpackage/share/IconTest.java on macosx-x64

Reviewed-by: bpb

! test/jdk/ProblemList.txt

Changeset: 42d9b1ba
Author:    Jan Lahoda <jlahoda at openjdk.org>
Date:      2021-12-08 18:50:38 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/42d9b1baac25df649a8d575f5ffa3a0d5b8e7ed0

8277106: Cannot compile certain sources with --release

Reviewed-by: darcy, mcimadamore

! make/data/symbols/java.base-C.sym.txt
! make/data/symbols/java.base-E.sym.txt
! make/data/symbols/java.base-G.sym.txt
! make/data/symbols/java.base-H.sym.txt
! make/data/symbols/java.xml-B.sym.txt
! make/data/symbols/java.xml-C.sym.txt
! make/data/symbols/java.xml-D.sym.txt
! make/data/symbols/java.xml-E.sym.txt
! make/data/symbols/jdk.incubator.foreign-F.sym.txt
! make/data/symbols/jdk.incubator.foreign-G.sym.txt
! make/data/symbols/jdk.incubator.foreign-H.sym.txt
! make/data/symbols/jdk.incubator.vector-G.sym.txt
! make/data/symbols/jdk.incubator.vector-H.sym.txt
! make/data/symbols/jdk.javadoc-H.sym.txt
! make/data/symbols/jdk.jfr-B.sym.txt
! make/data/symbols/jdk.jfr-G.sym.txt
! make/langtools/src/classes/build/tools/symbolgenerator/CreateSymbols.java
+ test/langtools/tools/javac/platform/NonExportedSuperTypes.java
! test/langtools/tools/javac/platform/createsymbols/CreateSymbolsTest.java
! test/langtools/tools/javac/platform/createsymbols/CreateSymbolsTestImpl.java

Changeset: fb11d8fa
Author:    Jonathan Gibbons <jjg at openjdk.org>
Date:      2021-12-08 19:48:05 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/fb11d8faf21539a8dc08d371658d1835484c8344

8272945: Use snippets in java.compiler documentation

Reviewed-by: erikj, alanb

! make/CompileInterimLangtools.gmk
! make/modules/java.compiler/Java.gmk
! src/java.compiler/share/classes/javax/tools/JavaCompiler.java
! src/java.compiler/share/classes/javax/tools/JavaFileManager.java
! src/java.compiler/share/classes/javax/tools/StandardJavaFileManager.java
! src/java.compiler/share/classes/javax/tools/package-info.java
+ src/java.compiler/share/classes/javax/tools/snippet-files/JavaSourceFromString.java

Changeset: 5a80abf7
Author:    Jonathan Gibbons <jjg at openjdk.org>
Date:      2021-12-08 19:50:14 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/5a80abf706dfde9342be53e78b942ff40f9624ea

8272944: Use snippets in jdk.javadoc documentation

Reviewed-by: hannesw

! src/jdk.compiler/share/classes/com/sun/tools/javac/model/JavacElements.java
! src/jdk.javadoc/share/classes/jdk/javadoc/doclet/package-info.java

Changeset: 8e8fadf2
Author:    Roger Riggs <rriggs at openjdk.org>
Date:      2021-12-08 20:37:41 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8e8fadf2d4e45f53286dd8424d95f733a12cd1a0

8278428: ObjectInputStream.readFully range check incorrect

Reviewed-by: alanb

! src/java.base/share/classes/java/io/ObjectInputStream.java
! test/jdk/java/io/Serializable/oldTests/WritePrimitive.java

Changeset: c83b781b
Author:    Daniel D. Daugherty <dcubed at openjdk.org>
Date:      2021-12-08 20:42:52 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/c83b781b6002ca0f067a35e678ab5285d98d015d

8278459: ProblemList javax/swing/JTree/4908142/bug4908142.java on macosx-aarch64

Reviewed-by: lmesnik, bpb, prr

! test/jdk/ProblemList.txt

Changeset: 6e7b7f35
Author:    Sergey Bylokhov <serb at openjdk.org>
Date:      2021-12-08 21:15:55 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/6e7b7f352e66c767b16e1e98a162e7fea79126c6

8278251: Enable "missing-explicit-ctor" check in the jdk.unsupported.desktop module

Reviewed-by: ihse, prr

- make/modules/jdk.unsupported.desktop/Java.gmk

Changeset: fe2ae8e3
Author:    Eamonn McManus <emcmanus at openjdk.org>
Date:      2021-12-08 21:24:43 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/fe2ae8e38bd8660cc637f13f425ccea17a11aa4f

8276904: Optional.toString() is unnecessarily expensive

Reviewed-by: rriggs, smarks

! src/java.base/share/classes/java/util/Optional.java
! src/java.base/share/classes/java/util/OptionalDouble.java
! src/java.base/share/classes/java/util/OptionalInt.java
! src/java.base/share/classes/java/util/OptionalLong.java

Changeset: b3faecf7
Author:    Roland Westrelin <roland at openjdk.org>
Date:      2021-12-08 21:33:33 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/b3faecf73966ce0435644a89f8f43d85720e8328

8276116: C2: optimize long range checks in int counted loops

Reviewed-by: kvn

! src/hotspot/cpu/x86/x86_32.ad
! src/hotspot/share/opto/compile.cpp
! src/hotspot/share/opto/loopTransform.cpp
! src/hotspot/share/opto/loopnode.cpp
! src/hotspot/share/opto/loopnode.hpp
! src/hotspot/share/opto/loopopts.cpp
! test/hotspot/jtreg/compiler/c2/irTests/TestLongRangeChecks.java
! test/hotspot/jtreg/compiler/rangechecks/TestLongRangeCheck.java

Changeset: 3893f4f7
Author:    Serguei Spitsyn <sspitsyn at openjdk.org>
Date:      2021-12-08 22:32:00 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3893f4f70b5828ee8e673ce7b1422877efe5c292

8278330: dump stack trace if the jvmti test nsk/jvmti/GetThreadState/thrstat002 is failed with wrong thread state

Reviewed-by: amenkov, lmesnik

! test/hotspot/jtreg/vmTestbase/nsk/jvmti/GetThreadState/thrstat002/thrstat002.cpp

Changeset: 03bf55f6
Author:    Vicente Romero <vromero at openjdk.org>
Date:      2021-12-08 22:49:43 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/03bf55f62065f8f9c8ade1eff8ca6eaeabe51450

8277980: ObjectMethods::bootstrap throws NPE when lookup is null

Reviewed-by: jjg

! src/java.base/share/classes/java/lang/runtime/ObjectMethods.java
! test/jdk/java/lang/runtime/ObjectMethodsTest.java

Changeset: 3cec700a
Author:    Roger Riggs <rriggs at openjdk.org>
Date:      2021-12-08 22:59:38 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3cec700a5caa2243772e4b01c40630cb044b76fc

8278463: [test] Serialization WritePrimitive test revised for readFully test fails

Reviewed-by: darcy

! test/jdk/java/io/Serializable/oldTests/WritePrimitive.java

Changeset: 83e6a4c0
Author:    Valerie Peng <valeriep at openjdk.org>
Date:      2021-12-08 23:04:15 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/83e6a4c0e9e4a9474ae0c1252378b1a09d1d2df0

8255409: Support the new C_GetInterfaceList, C_GetInterface, and C_SessionCancel APIs in PKCS#11 v3.0

Reviewed-by: ascarpino, weijun

! src/jdk.crypto.cryptoki/share/classes/sun/security/pkcs11/Config.java
! src/jdk.crypto.cryptoki/share/classes/sun/security/pkcs11/P11AEADCipher.java
! src/jdk.crypto.cryptoki/share/classes/sun/security/pkcs11/P11Cipher.java
! src/jdk.crypto.cryptoki/share/classes/sun/security/pkcs11/P11KeyWrapCipher.java
! src/jdk.crypto.cryptoki/share/classes/sun/security/pkcs11/P11Mac.java
! src/jdk.crypto.cryptoki/share/classes/sun/security/pkcs11/P11PSSSignature.java
! src/jdk.crypto.cryptoki/share/classes/sun/security/pkcs11/P11RSACipher.java
! src/jdk.crypto.cryptoki/share/classes/sun/security/pkcs11/P11Signature.java
! src/jdk.crypto.cryptoki/share/classes/sun/security/pkcs11/P11Util.java
! src/jdk.crypto.cryptoki/share/classes/sun/security/pkcs11/SunPKCS11.java
! src/jdk.crypto.cryptoki/share/classes/sun/security/pkcs11/wrapper/PKCS11.java
! src/jdk.crypto.cryptoki/share/native/libj2pkcs11/p11_sessmgmt.c
! src/jdk.crypto.cryptoki/share/native/libj2pkcs11/p11_util.c
! src/jdk.crypto.cryptoki/share/native/libj2pkcs11/pkcs11wrapper.h
! src/jdk.crypto.cryptoki/unix/native/libj2pkcs11/p11_md.c
! src/jdk.crypto.cryptoki/unix/native/libj2pkcs11/p11_md.h
! src/jdk.crypto.cryptoki/windows/native/libj2pkcs11/p11_md.c
! src/jdk.crypto.cryptoki/windows/native/libj2pkcs11/p11_md.h

Changeset: 35243558
Author:    Zhiqiang Zang <capapoc at gmail.com>
Committer: Igor Veresov <iveresov at openjdk.org>
Date:      2021-12-09 00:18:59 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/352435581e4354741684d66df8a33b1fbdb96162

8277882: New subnode ideal optimization: converting "c0 - (x + c1)" into "(c0 - c1) - x"

Reviewed-by: dlong, iveresov

! src/hotspot/share/opto/subnode.cpp
+ test/hotspot/jtreg/compiler/c2/TestSubIdealC0Minus_YPlusC1_.java
+ test/micro/org/openjdk/bench/vm/compiler/SubIdealC0Minus_YPlusC1_.java

Changeset: 8ef1a232
Author:    Alexey Semenyuk <asemenyuk at openjdk.org>
Date:      2021-12-09 02:31:29 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8ef1a232b100dbac72356ca4844d01964f3d5287

8278311: Debian packaging doesn't work

Reviewed-by: almatvee

! src/jdk.jpackage/share/classes/jdk/jpackage/internal/OverridableResource.java
! test/jdk/tools/jpackage/junit/jdk/jpackage/internal/OverridableResourceTest.java

Changeset: d1706828
Author:    Jonathan Gibbons <jjg at openjdk.org>
Date:      2021-12-09 02:53:52 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/d1706828fb6a95ecad2bab4112b2e1a7d3319df8

8278466: "spurious markup" warnings in snippets when building `docs-reference`

Reviewed-by: darcy

! src/java.compiler/share/classes/javax/tools/JavaFileManager.java
! src/java.compiler/share/classes/javax/tools/StandardJavaFileManager.java

Changeset: 62a7f5d3
Author:    Aleksey Shipilev <shade at openjdk.org>
Date:      2021-12-09 06:50:56 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/62a7f5d3236ab2248518a475b1d8b71cb4bf1313

8254318: Remove .hgtags

Reviewed-by: erikj, xliu

- .hgtags

Changeset: 1ea766db
Author:    Markus Gr?nlund <mgronlun at openjdk.org>
Date:      2021-12-09 09:23:39 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/1ea766db5519f03e36fc5b0c446cf34b172bb349

8278419: JFR jcmd option contract "This value cannot be changed once JFR has been initialized" is not enforced

Reviewed-by: egahlin

! src/hotspot/share/jfr/dcmd/jfrDcmds.cpp
+ test/jdk/jdk/jfr/jcmd/TestJcmdConfigureReadOnly.java

Changeset: 84baea75
Author:    Julia Boes <jboes at openjdk.org>
Date:      2021-12-09 09:29:08 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/84baea753a01428d9dc5befa5f23d4ac853a7bbc

8278433: Use snippets in jdk.incubator.foreign documentation

Reviewed-by: mcimadamore

! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/CLinker.java
! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/MemoryAddress.java
! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/MemoryHandles.java
! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/MemoryLayout.java
! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/MemorySegment.java
! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/ResourceScope.java
! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/SegmentAllocator.java
! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/SequenceLayout.java
! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/ValueLayout.java
! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/package-info.java

Changeset: 965ea8d9
Author:    Markus Gr?nlund <mgronlun at openjdk.org>
Date:      2021-12-09 09:29:59 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/965ea8d9cd29aee41ba2b1b0b0c67bb67eca22dd

8274298: JFR Thread Sampler thread must not acquire malloc lock after suspending a thread because of possible deadlock

Reviewed-by: egahlin

! src/hotspot/share/jfr/periodic/sampling/jfrThreadSampler.cpp
! src/hotspot/share/jfr/periodic/sampling/jfrThreadSampler.hpp
! src/hotspot/share/jfr/recorder/checkpoint/types/traceid/jfrTraceIdKlassQueue.cpp
! src/hotspot/share/jfr/recorder/checkpoint/types/traceid/jfrTraceIdKlassQueue.hpp
! src/hotspot/share/jfr/recorder/checkpoint/types/traceid/jfrTraceIdLoadBarrier.cpp
! src/hotspot/share/jfr/recorder/checkpoint/types/traceid/jfrTraceIdLoadBarrier.hpp
! src/hotspot/share/jfr/recorder/stacktrace/jfrStackTrace.cpp
! src/hotspot/share/jfr/utilities/jfrEpochQueue.hpp
! src/hotspot/share/jfr/utilities/jfrEpochQueue.inline.hpp

Changeset: 08aad850
Author:    Erik Gahlin <egahlin at openjdk.org>
Date:      2021-12-09 14:13:53 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/08aad8506e60157fc5ee1cc0e3e90cf1c35b3df5

8211230: JFR: internal events

Reviewed-by: mgronlun

! make/src/classes/build/tools/jfr/GenerateJfrFiles.java
! src/hotspot/share/jfr/jni/jfrUpcalls.cpp
! src/hotspot/share/jfr/jni/jfrUpcalls.hpp
! src/hotspot/share/jfr/metadata/metadata.xml
! src/hotspot/share/jfr/metadata/metadata.xsd
! src/hotspot/share/jfr/recorder/checkpoint/jfrMetadataEvent.cpp
! src/hotspot/share/jfr/recorder/jfrEventSetting.cpp
! src/hotspot/share/jfr/recorder/jfrEventSetting.hpp
! src/jdk.jfr/share/classes/jdk/jfr/EventType.java
! src/jdk.jfr/share/classes/jdk/jfr/FlightRecorderPermission.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/EventControl.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/JVMUpcalls.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/MetadataLoader.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/MetadataRepository.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/PrivateAccess.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/Type.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/TypeLibrary.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/tool/Metadata.java
! src/jdk.jfr/share/conf/jfr/default.jfc
! src/jdk.jfr/share/conf/jfr/profile.jfc

Changeset: 6dae52f8
Author:    Eric Liu <eliu at openjdk.org>
Committer: Ningsheng Jian <njian at openjdk.org>
Date:      2021-12-09 14:16:38 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/6dae52f8e3993d529033147de8e34ad1e7d48c53

8276985: AArch64: [vectorapi] Backend support of VectorMaskToLongNode

Reviewed-by: njian, aph

! src/hotspot/cpu/aarch64/aarch64_neon.ad
! src/hotspot/cpu/aarch64/aarch64_neon_ad.m4
! src/hotspot/cpu/aarch64/aarch64_sve.ad
! src/hotspot/cpu/aarch64/aarch64_sve_ad.m4
! src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp
! src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp

Changeset: 09831e7a
Author:    Joe Darcy <darcy at openjdk.org>
Committer: Jesper Wilhelmsson <jwilhelm at openjdk.org>
Date:      2021-12-09 17:01:59 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/09831e7aa47ebe41eab2f3014ebbacf338097ef6

8273146: Start of release updates for JDK 19
8277511: Add SourceVersion.RELEASE_19
8277513: Add source 19 and target 19 to javac

Reviewed-by: dholmes, alanb, erikj, iris, mikael, ihse

! make/conf/version-numbers.conf
+ make/data/symbols/java.base-I.sym.txt
+ make/data/symbols/java.compiler-I.sym.txt
+ make/data/symbols/java.datatransfer-I.sym.txt
+ make/data/symbols/java.desktop-I.sym.txt
= make/data/symbols/java.instrument-I.sym.txt
+ make/data/symbols/java.logging-I.sym.txt
+ make/data/symbols/java.management-I.sym.txt
= make/data/symbols/java.management.rmi-I.sym.txt
+ make/data/symbols/java.naming-I.sym.txt
+ make/data/symbols/java.net.http-I.sym.txt
+ make/data/symbols/java.rmi-I.sym.txt
= make/data/symbols/java.scripting-I.sym.txt
= make/data/symbols/java.security.jgss-I.sym.txt
= make/data/symbols/java.security.sasl-I.sym.txt
= make/data/symbols/java.smartcardio-I.sym.txt
= make/data/symbols/java.sql-I.sym.txt
= make/data/symbols/java.sql.rowset-I.sym.txt
+ make/data/symbols/java.xml-I.sym.txt
+ make/data/symbols/java.xml.crypto-I.sym.txt
+ make/data/symbols/jdk.accessibility-I.sym.txt
= make/data/symbols/jdk.attach-I.sym.txt
+ make/data/symbols/jdk.compiler-I.sym.txt
= make/data/symbols/jdk.dynalink-I.sym.txt
+ make/data/symbols/jdk.httpserver-I.sym.txt
+ make/data/symbols/jdk.incubator.foreign-I.sym.txt
+ make/data/symbols/jdk.incubator.vector-I.sym.txt
= make/data/symbols/jdk.jartool-I.sym.txt
+ make/data/symbols/jdk.javadoc-I.sym.txt
= make/data/symbols/jdk.jconsole-I.sym.txt
= make/data/symbols/jdk.jdi-I.sym.txt
+ make/data/symbols/jdk.jlink-I.sym.txt
+ make/data/symbols/jdk.jshell-I.sym.txt
= make/data/symbols/jdk.jsobject-I.sym.txt
= make/data/symbols/jdk.management-I.sym.txt
+ make/data/symbols/jdk.management.jfr-I.sym.txt
= make/data/symbols/jdk.net-I.sym.txt
= make/data/symbols/jdk.sctp-I.sym.txt
= make/data/symbols/jdk.security.auth-I.sym.txt
+ make/data/symbols/jdk.security.jgss-I.sym.txt
+ make/data/symbols/jdk.unsupported-I.sym.txt
= make/data/symbols/jdk.xml.dom-I.sym.txt
! make/data/symbols/symbols
! src/hotspot/share/classfile/classFileParser.cpp
! src/java.base/share/classes/jdk/internal/org/objectweb/asm/ClassReader.java
! src/java.base/share/classes/jdk/internal/org/objectweb/asm/Opcodes.java
! src/java.compiler/share/classes/javax/lang/model/SourceVersion.java
! src/java.compiler/share/classes/javax/lang/model/util/AbstractAnnotationValueVisitor14.java
! src/java.compiler/share/classes/javax/lang/model/util/AbstractElementVisitor14.java
! src/java.compiler/share/classes/javax/lang/model/util/AbstractTypeVisitor14.java
! src/java.compiler/share/classes/javax/lang/model/util/ElementKindVisitor14.java
! src/java.compiler/share/classes/javax/lang/model/util/ElementScanner14.java
! src/java.compiler/share/classes/javax/lang/model/util/SimpleAnnotationValueVisitor14.java
! src/java.compiler/share/classes/javax/lang/model/util/SimpleElementVisitor14.java
! src/java.compiler/share/classes/javax/lang/model/util/SimpleTypeVisitor14.java
! src/java.compiler/share/classes/javax/lang/model/util/TypeKindVisitor14.java
! src/jdk.compiler/share/classes/com/sun/tools/javac/code/Source.java
! src/jdk.compiler/share/classes/com/sun/tools/javac/jvm/ClassFile.java
! src/jdk.compiler/share/classes/com/sun/tools/javac/jvm/Target.java
! src/jdk.compiler/share/classes/com/sun/tools/javac/processing/PrintingProcessor.java
! test/hotspot/jtreg/runtime/CommandLine/VMDeprecatedOptions.java
! test/langtools/tools/javac/api/TestGetSourceVersions.java
! test/langtools/tools/javac/classfiles/ClassVersionChecker.java
! test/langtools/tools/javac/lib/JavacTestingAbstractProcessor.java
! test/langtools/tools/javac/preview/classReaderTest/Client.nopreview.out
! test/langtools/tools/javac/preview/classReaderTest/Client.preview.out
! test/langtools/tools/javac/versions/Versions.java

Changeset: 01b30bfa
Author:    Martin Doerr <mdoerr at openjdk.org>
Date:      2021-12-09 17:04:55 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/01b30bfa99e95cf1e9209c8de1f3c3c762596708

8253860: PPC: Relocation::pd_set_data_value conflates compressed oops and klasses

Reviewed-by: dlong, rrich

! src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp
! src/hotspot/cpu/ppc/macroAssembler_ppc.cpp
! src/hotspot/cpu/ppc/nativeInst_ppc.hpp
! src/hotspot/cpu/ppc/ppc.ad
! src/hotspot/cpu/ppc/relocInfo_ppc.cpp

Changeset: bc31ccc9
Author:    Michael McMahon <michaelm at openjdk.org>
Date:      2021-12-09 17:38:49 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/bc31ccc95be9523cc6c64932f6d39f81c2e82bdd

8278312: Update SimpleSSLContext keystore to use SANs for localhost IP addresses

Reviewed-by: dfuchs

+ test/jdk/com/sun/net/httpserver/SANTest.java
! test/jdk/java/net/httpclient/http2/server/Http2TestServer.java
! test/lib/jdk/test/lib/net/testkeys

Changeset: abebde74
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-12-09 18:15:53 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/abebde74409e87f4bab2e72ed27a2524a13611da

8278421: G1: Remove unused HeapRegion::verify

Reviewed-by: iwalulya, tschatzl

! src/hotspot/share/gc/g1/heapRegion.cpp
! src/hotspot/share/gc/g1/heapRegion.hpp

Changeset: fcd67a52
Author:    Toshio Nakamura <tnakamura at openjdk.org>
Committer: Naoto Sato <naoto at openjdk.org>
Date:      2021-12-09 19:05:31 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/fcd67a5242b7db06e4cb06b574972a463b209b2e

8278185: Custom JRE cannot find non-ASCII named module inside

Reviewed-by: naoto

! src/java.base/share/classes/jdk/internal/jimage/ImageStringsReader.java
+ test/jdk/tools/jimage/JImageNonAsciiNameTest.java

Changeset: 918b3505
Author:    Jonathan Gibbons <jjg at openjdk.org>
Date:      2021-12-09 21:47:50 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/918b3505e1cbbf5ac380cbcca43aae2829c18a2d

8278516: Typos in snippet for java.compiler

Reviewed-by: darcy

! src/java.compiler/share/classes/javax/tools/StandardJavaFileManager.java

Changeset: d40e90b4
Author:    Daniel D. Daugherty <dcubed at openjdk.org>
Date:      2021-12-09 22:03:04 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/d40e90b4a1b55753a178d824c4c60209bc46efac

8278521: ProblemList java/lang/management/ThreadMXBean/ThreadLists.java

Reviewed-by: bpb

! test/jdk/ProblemList.txt

Changeset: ec0a5ac8
Author:    Jesper Wilhelmsson <jwilhelm at openjdk.org>
Date:      2021-12-09 23:24:40 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ec0a5ac8fec75c5c3eda3d9909d2e65d610d9854

Merge


Changeset: 066b348d
Author:    Kim Barrett <kbarrett at openjdk.org>
Date:      2021-12-10 01:32:05 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/066b348dbc989cf90048b136a8b42a0ea1cd08d7

8277807: Increase default initial concurrent refinement threshold

Reviewed-by: tschatzl, sjohanss

! src/hotspot/share/gc/g1/g1ConcurrentRefine.cpp

Changeset: f29745db
Author:    Fei Yang <felix.yang at huawei.com>
Date:      2021-12-09 20:39:54 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f29745db46fecb5f5dcc93930bb1f1c9f8032fe9

Merge branch 'master' into riscv-port

! src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp
! src/hotspot/share/runtime/arguments.cpp
! src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp
! src/hotspot/share/runtime/arguments.cpp


From fjiang at openjdk.java.net  Fri Dec 10 01:51:33 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Fri, 10 Dec 2021 01:51:33 GMT
Subject: [riscv-port] Integrated: 8278531: riscv: Remove duplicate code
 bitset_to_fregs
In-Reply-To: <V8NSAQOmj4mS9o9RloTI42a6JBXf8OWzrPXelhH1LiI=.89c2be1b-e780-4411-b29e-45bb3152b65e@github.com>
References: <V8NSAQOmj4mS9o9RloTI42a6JBXf8OWzrPXelhH1LiI=.89c2be1b-e780-4411-b29e-45bb3152b65e@github.com>
Message-ID: <wtARGu89yUIHx8mVoqe34yiRUsXrrTTsxGi-mvajqgk=.41ef3072-1821-4427-b183-2b07a0f20fc0@github.com>

On Fri, 10 Dec 2021 01:18:58 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> After [JDK-8278337](https://bugs.openjdk.java.net/browse/JDK-8278337), the definition of `bitset_to_fregs` is just same as `bitset_to_regs`.
> 
> Hotspot and jdk tier1 passed on the unmatched board. All tests were tested without new failures.

This pull request has now been integrated.

Changeset: e7d712c8
Author:    Feilong Jiang <fjiang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/e7d712c8e8ceb759ed8906706ff2b06996417a5e
Stats:     17 lines in 2 files changed: 0 ins; 14 del; 3 mod

8278531: riscv: Remove duplicate code bitset_to_fregs

Reviewed-by: fyang

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/28

From felix.yang at huawei.com  Fri Dec 10 02:53:06 2021
From: felix.yang at huawei.com (Yangfei (Felix))
Date: Fri, 10 Dec 2021 02:53:06 +0000
Subject: CFV: New RISC-V Port Committer: Yadong Wang
Message-ID: <125ba4f953a9441c847a749503b271ef@huawei.com>

I hereby nominate Yadong Wang (yadongwang) to RISC-V Port Committer.

Yadong is the main developer of OpenJDK riscv-port since the beginning of this project. He has contributed 10 patches to JDK and RISC-V Port.
These references in JDK and RISC-V Port projects justify the call to make him a RISC-V Port Committer.

Votes are due by 9:00 UTC on Friday 24, December 2021.

Only current RISC-V Port Committer[1] are eligible to vote on this nomination.
Votes must be cast in the open replying to this mailing list.

For Lazy Consensus voting instructions, see[2].

[1] https://openjdk.java.net/census 
[2] https://openjdk.java.net/projects/#committer-vote 

Thanks,
Felix

=========

8247979: aarch64: missing side effect of killing flags for clearArray_reg_reg
8264096: slowdebug jvm crashes when StrInflatedCopy match rule is not supported
8276792: RISC-V Port: Initial support for RV64GV
8277430: riscv: Refactor interpreter native wrappers
8277431: riscv: Intrinsify recursive ObjectMonitor locking for C2
8277508: need to check has_predicated_vectors before calling scalable_predicate_reg_slots
8277877: C2 fast_unlock intrinsic on riscv has unnecessary ownership check
8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate
8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2
8278387: riscv: Implement UseHeavyMonitors consistently

From felix.yang at huawei.com  Fri Dec 10 02:55:03 2021
From: felix.yang at huawei.com (Yangfei (Felix))
Date: Fri, 10 Dec 2021 02:55:03 +0000
Subject: CFV: New RISC-V Port Committer: Yadong Wang
Message-ID: <65325f03310b4d92b4809c0d21d5c6ac@huawei.com>

Vote: yes

> -----Original Message-----
> From: Yangfei (Felix)
> Sent: Friday, December 10, 2021 10:53 AM
> To: riscv-port-dev at openjdk.java.net
> Subject: CFV: New RISC-V Port Committer: Yadong Wang
> 
> I hereby nominate Yadong Wang (yadongwang) to RISC-V Port Committer.
> 
> Yadong is the main developer of OpenJDK riscv-port since the beginning of
> this project. He has contributed 10 patches to JDK and RISC-V Port.
> These references in JDK and RISC-V Port projects justify the call to make him
> a RISC-V Port Committer.
> 
> Votes are due by 9:00 UTC on Friday 24, December 2021.
> 
> Only current RISC-V Port Committer[1] are eligible to vote on this nomination.
> Votes must be cast in the open replying to this mailing list.
> 
> For Lazy Consensus voting instructions, see[2].
> 
> [1] https://openjdk.java.net/census
> [2] https://openjdk.java.net/projects/#committer-vote
> 
> Thanks,
> Felix
> 
> =========
> 
> 8247979: aarch64: missing side effect of killing flags for clearArray_reg_reg
> 8264096: slowdebug jvm crashes when StrInflatedCopy match rule is not
> supported
> 8276792: RISC-V Port: Initial support for RV64GV
> 8277430: riscv: Refactor interpreter native wrappers
> 8277431: riscv: Intrinsify recursive ObjectMonitor locking for C2
> 8277508: need to check has_predicated_vectors before calling
> scalable_predicate_reg_slots
> 8277877: C2 fast_unlock intrinsic on riscv has unnecessary ownership check
> 8277890: riscv: fix the infinite LR/SC loop in
> BarrierSetAssembler::eden_allocate
> 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2
> 8278387: riscv: Implement UseHeavyMonitors consistently

From edward.nevill at gmail.com  Fri Dec 10 08:06:21 2021
From: edward.nevill at gmail.com (Edward Nevill)
Date: Fri, 10 Dec 2021 08:06:21 +0000
Subject: CFV: New RISC-V Port Committer: Yadong Wang
In-Reply-To: <125ba4f953a9441c847a749503b271ef@huawei.com>
References: <125ba4f953a9441c847a749503b271ef@huawei.com>
Message-ID: <cd89a481945f8942959a55ece6a7f27256b110bf.camel@gmail.com>

Vote: Yes

On Fri, 2021-12-10 at 02:53 +0000, Yangfei (Felix) wrote:
> I hereby nominate Yadong Wang (yadongwang) to RISC-V Port Committer.
> 
> Yadong is the main developer of OpenJDK riscv-port since the
> beginning of this project. He has contributed 10 patches to JDK and
> RISC-V Port.
> These references in JDK and RISC-V Port projects justify the call to
> make him a RISC-V Port Committer.
> 
> Votes are due by 9:00 UTC on Friday 24, December 2021.
> 
> Only current RISC-V Port Committer[1] are eligible to vote on this
> nomination.
> Votes must be cast in the open replying to this mailing list.
> 
> For Lazy Consensus voting instructions, see[2].
> 
> [1] https://openjdk.java.net/census 
> [2] https://openjdk.java.net/projects/#committer-vote 
> 
> Thanks,
> Felix
> 
> =========
> 
> 8247979: aarch64: missing side effect of killing flags for
> clearArray_reg_reg
> 8264096: slowdebug jvm crashes when StrInflatedCopy match rule is not
> supported
> 8276792: RISC-V Port: Initial support for RV64GV
> 8277430: riscv: Refactor interpreter native wrappers
> 8277431: riscv: Intrinsify recursive ObjectMonitor locking for C2
> 8277508: need to check has_predicated_vectors before calling
> scalable_predicate_reg_slots
> 8277877: C2 fast_unlock intrinsic on riscv has unnecessary ownership
> check
> 8277890: riscv: fix the infinite LR/SC loop in
> BarrierSetAssembler::eden_allocate
> 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2
> 8278387: riscv: Implement UseHeavyMonitors consistently


From felix.yang at huawei.com  Fri Dec 10 09:13:28 2021
From: felix.yang at huawei.com (Yangfei (Felix))
Date: Fri, 10 Dec 2021 09:13:28 +0000
Subject: Test mail service for this list
Message-ID: <cf89127a0dd24348b66673fdb1682ac1@huawei.com>

Please ignore.

From fyang at openjdk.java.net  Fri Dec 10 09:31:42 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Fri, 10 Dec 2021 09:31:42 GMT
Subject: [riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine
 flags register in C2 [v2]
In-Reply-To: <6nmr2Yh797p1XjsyRDfGIqp6WfDbJk-o1dR6mTuxbQk=.d1f741ba-bda9-4228-8cb0-43d0e23b0f32@github.com>
References: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>
 <6nmr2Yh797p1XjsyRDfGIqp6WfDbJk-o1dR6mTuxbQk=.d1f741ba-bda9-4228-8cb0-43d0e23b0f32@github.com>
Message-ID: <PFmNGxlBK8PHTVklKwa-T-ez0Z3T1vLFHhvlkXEjNhY=.7b41e193-639d-49a1-a098-47ae959b23ae@github.com>

On Wed, 1 Dec 2021 09:35:26 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

>> There are non-allocatable registers t0 and t1 in C2, frequently used as temporary registers for common code snipptes. Meanwhile, C2 use t1 as the flags register, so that many instructs using t1 as a temporary register must declare the data flow effect of t1 which is not part of a match rule. So we can reserve t2 and use it as the machine flags register in C2 instead, to reduce the probability of misuse of t1 without declaring the data flow effect.
>
> Yadong Wang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   8278041: riscv: Use t2 as the dedicated machine flags register in C2(2)

Let's keep the current implementation for some time to see :-)

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/21

From shade at redhat.com  Fri Dec 10 15:56:22 2021
From: shade at redhat.com (Aleksey Shipilev)
Date: Fri, 10 Dec 2021 16:56:22 +0100
Subject: CFV: New RISC-V Port Committer: Yadong Wang
In-Reply-To: <125ba4f953a9441c847a749503b271ef@huawei.com>
References: <125ba4f953a9441c847a749503b271ef@huawei.com>
Message-ID: <16771b91-e992-3b33-86bd-574d8eb55852@redhat.com>

Vote: yes

On 12/10/21 3:53 AM, Yangfei (Felix) wrote:
> I hereby nominate Yadong Wang (yadongwang) to RISC-V Port Committer.

-- 
Thanks,
-Aleksey


From fyang at openjdk.java.net  Thu Dec  9 05:04:17 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Thu, 9 Dec 2021 05:04:17 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <yqM8SRigjZfjjBoYVXDGtkDE2lqOECMoy86RMYEoe9k=.8456d733-5049-4f32-8aab-90fa08c667e0@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
 <yqM8SRigjZfjjBoYVXDGtkDE2lqOECMoy86RMYEoe9k=.8456d733-5049-4f32-8aab-90fa08c667e0@github.com>
Message-ID: <4To71m1jS-vP-OLwWS3zOg3l_HWxoz1An_mv071UrlA=.3516037c-cc03-4fcd-badf-9b326635ffca@github.com>

On Thu, 9 Dec 2021 03:54:19 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> ### About our first scheme:
> We may mark some instructions as compressible by adding function arguments. But compressed instructions can be used in almost every place in the code cache, like C1, C2, interpreter, and stub code. The range is quite big -- for instance, after some time we may want to compress some intrinsics, say, `C2_MacroAssembler::string_indexof_char_short()`.
>
> After `addi(Rd, Rs, imm)` becomes `addi(Rd, Rs, imm, bool compressible)`, it will be
>
> ```
> bind(MATCH1);
> addi(index, index, 1);   ->    addi(index, index, 1, true);
> j(MATCH);                ->    j(MATCH, true);
>
> bind(MATCH2);
> addi(index, index, 2);   ->    addi(index, index, 2, true);
> j(MATCH);                ->    j(MATCH, true)
>
> bind(MATCH3);
> addi(index, index, 3);   ->   ...
> j(MATCH);
>
> bind(MATCH4);
> addi(index, index, 4);
> j(MATCH);
>
> bind(MATCH5);
> addi(index, index, 5);
> j(MATCH);
> ```

That's exactly what I mean :-)
And this could be carried out incrementally, module by module.

> We might not add extra explicit arguments to them since this may make maintenance quite hard. :-)

No. Passing one extra argument here won't affect future code maintainance in anyway here.
In fact, I think this will make reviewer/maintainer's life easier since this makes it explict the places where it's safe to do compress.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24


From xlinzheng at openjdk.java.net  Thu Dec  9 03:57:31 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Thu, 9 Dec 2021 03:57:31 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
Message-ID: <yqM8SRigjZfjjBoYVXDGtkDE2lqOECMoy86RMYEoe9k=.8456d733-5049-4f32-8aab-90fa08c667e0@github.com>

On Tue, 7 Dec 2021 04:46:10 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
>
> This patch support RISC-V RVC extension. It can introduce:
> * 21% code size reduction in template interpreter generated code
> * 20%~25% code size reduction in C1 generated code, evaluated by a common SpringBoot program
> * 15%~20% code size reduction in C2 generated code, evaluated by a common SpringBoot program
>
> In my observation, the code size footprint could be reduced to nearly a level of the AArch64 back-end. About the performance, there seems a stable ~0.7% performance improvement on SPECjbb2015 on one HiFive Unleashed board, considering the code density increase. I think the performance aspect might be a speculative behavior on different hardware implementations because C910's performance might be better than that, but HiFive Unleashed may be more general.
>
> Things about this patch:
> * If an instruction is compressible, then we will implicitly emit a 16-bit compressed instruction instead of the 32-bit instruction in Assembler.
> * About the `_nc` postfix of some of Assembler instructions: we know a bunch of places should be reserved for patching, where we cannot change them into compressed instructions. `_nc` is short for `not compressible` - with this, those instructions should keep their origin 4-byte form and remain uncompressed.
> * There are things not easy to compress like MachBranchNodes. Please see the comments in the code - currently this patch does not support this. We will support this improvement in patches coming afterward.
>
> The macros after their expansion might be like:
>
> void andr(Register Rd, Register Rs1, Register Rs2) {
> +  {
> +    Register src = noreg;
> +    if (UseRVC && Rs1->is_compressed_valid() && Rs2->is_compressed_valid() &&
> +        ((src = Rs1, Rs2 == Rd) || (src = Rs2, Rs1 == Rd))) {
> +      and_c(Rd, src);
> +      return;
> +    }
> +  }
>   unsigned insn = 0;
>   patch((address)&insn, 6, 0, 0b0110011);
>   patch((address)&insn, 14, 12, 0b111);
>   patch((address)&insn, 31, 25, 0b0000000);
>   patch_reg((address)&insn, 7, Rd);
>   patch_reg((address)&insn, 15, Rs1);
>   patch_reg((address)&insn, 20, Rs2);
>   emit(insn);
> };
>
>
> For further information, please see comments in `assembler_riscv_cext.hpp`.
>
> --
>
> This patch may need some time to acquire a review. I have been polishing this patch for quite a long time and it might seem stable under a bunch of full-tier tests and some tier1 jdk/hotspot jtreg tests. But I think we might mark it `experimental` at first, though it is turned on by default. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/7), just for reference, might be quite different from the current one.
>
> I am pleased to receive any suggestion.
>
> Thanks,
> Xiaolin

Thanks for your reviews, Felix and Yadong, and also thanks for your advice -- also quite sorry for the late reply.

I think I totally understand your concerns.

Firstly please let me talk about my opinion about this.
Most compressible instructions could be safely compressed, say, ~25% of total RISCV instructions, except only several places like
1. patchable code, for instance: `la_patchable` related code;
2. and several places requiring a fixed length like `BoxLockNode`.
We have found these places, excluded them in this patch, and wrapped them for developers into `ld_patchable`, `jalr_patchable` in this patch. If you feel unsafe for misuse from developers, maybe we can further carry out some strong guarantees to prevent this from happening. We can disable `UseRVC` by default for now, the jvm shoud be same behavior as before. And after enough testing, we can have more confidence to enable it.


I think your suggestions are indeed reasonable in your aspects, for safety.

-----

### About our first scheme:

We may mark some instructions as compressible by adding function arguments. But compressed instructions can be used in almost every place in the code cache, like C1, C2, interpreter, and stub code. The range is quite big -- for instance, after some time we may want to compress some intrinsics, say, `C2_MacroAssembler::string_indexof_char_short()`.

After `addi(Rd, Rs, imm)` becomes `addi(Rd, Rs, imm, bool compressible)`, it will be


bind(MATCH1);
addi(index, index, 1);   ->    addi(index, index, 1, true);
j(MATCH);                ->    j(MATCH, true);

bind(MATCH2);
addi(index, index, 2);   ->    addi(index, index, 2, true);
j(MATCH);                ->    j(MATCH, true)

bind(MATCH3);
addi(index, index, 3);   ->   ...
j(MATCH);

bind(MATCH4);
addi(index, index, 4);
j(MATCH);

bind(MATCH5);
addi(index, index, 5);
j(MATCH);

We might not add extra explicit arguments to them since this may make maintenance quite hard. :-)

-----
### About our second scheme:

Considering the `CompressibleRegion` solution, this could indeed, largely expand the range of code included. But we may face some situations:

As code function and features begin to complete, we may continue to make code compress further denser afterward. If we want to use this region to include a quite large range of function, of which we think is safe to compress.


#define __ _masm->
intrinsic A()
{
CompressibleRegion cr;                 // The CompressibleRegion

.. balabala ...
.. balabala ...
__ macroassembler_function();          // Here may include a tiny 'la_patchable'
.. balabala ...
.. balabala ...
}


Inside the `macroassembler_function()`, a `la_patchable` might be hidden somewhere...
What should we do? It seems that we need another `UncompressibleRegion ur` to exclude such a smaller region.


#define __ _masm->
intrinsic A()
{
CompressibleRegion cr;

.. balabala ...
.. balabala ...
{
UncompressibleRegion ur;             // Add one UncompressibleRegion
__ macroassembler_function();
}
.. balabala ...
.. balabala ...
}


As the inherent laws of things, the number of `CompressibleRegion` will inevitably become more and more; the same pattern emerges one by one; hence, the `CompressibleRegion` may fly to every part of the world; hmm, we may think naturally: why don't we remove the `CompressibleRegion` and remain the `UncompressibleRegion`? Because it seems most of the code could get compressed, and only several places could not be compressed. Why not maintain a blacklist for them? ...

So comes

#define __ _masm->
intrinsic A()
{
.. balabala ... (automatically compressed)
.. balabala ... (automatically compressed)
{
__ macroassembler_function_nc();               // nc things :-)
}
.. balabala ... (automatically compressed)
.. balabala ... (automatically compressed)
}


I think finally it may become the solution of this patch (i.e. the blacklist)... :-)

I hope this analysis is reasonable and it could bring you some smiles.

In that the blacklist must be the core of exclusions, I might recommend focusing on the maintenance of the blacklist, because anyway, we might face the blacklist in the future. To relieve your concerns, maybe making `UseRVC` false as default for now is a better plan because it is an one-click switch.

But, to step back, I totally understand your points as well. If you still consider the whitelist scheme might be a good scheme for you, I will choose to use your scheme for now, and add the `CompressibleRegion` and `UncompressibleRegion` gradually. But I assume maybe turning `UseRVC` as false could better solve this?

-----
### About splitting the patch:

Let's come back to our topic. I have considered from your angle and I begin to realize this design might be quite counterintuitive for guys who always use the normal 4-byte instructions to work; and also because of this 'blacklist' mode, which may cause a burden for reviewers to review. But I believe the primary part (the definitions of C-Ext, like `c.j/c.beqz/c.add`... stuff) could be trivial and this could be separated as a primitive patch -- it may relieve the burden for the reviewers.

-----
### About an ideal but specious solution:

In fact, I think the ideal solution might be to use another brandy-new pass to handle this compression logic, at the end of C1's `Compilation::emit_code_body`, C2's `PhaseOutput`, and other `BufferBlobs`' end of emission, to compress instructions in batches after all instructions have emitted to `CodeBlob`s. I think it will prevent all the above-mentioned issues: no hard-to-understand `_nc` things, no black and white lists, and programmers have no need to care about whether there is C-Ext or not. But it might be very difficult and specious:
* First, we need to re-do all relocations, check all paddings like `CodeEntryAlignment`, `OptoLoopAlignment`... also self-written `__ align()`s. If developers want to add ten `nops` to align addresses, I think we lack knowledge about these things just before code installation and make the code not 'what they see is what they get'.
* Second, we need to re-do all `OopMap`s and other related stuff. These delicate data structures are precisely calculated by C2's `BuildOopMaps()`. If we insert a phase at the end of all phases to compress code, it will be no less than doing these stuff once again. Also, for modifying those maps and debuginfos, maybe we need to add APIs to change the data inside them. This will further cause invasions to the public codebase just because RISC-V has this extension -- maybe other guys will not allow us to do such a big change. Besides, I speculate that it should be limited to our back-end only.

I consider this strategy has other limits except for those above-mentioned ones. So I did not choose this plan.

-----

It might be so energy-consuming for me to write so many words in English to explain my reasoning and write analysis in detail. If there are some typos or errors, please don't mind. I wonder if is there a need to arrange a small meeting or not -- we may need to split the patch, discuss friendly about solutions and precautions, and gradually reach a consensus. I think for this patch, we might finally reach that place.



Thanks again for your reviews and advice.

Sincerely,
Xiaolin

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24


From yadongwang at openjdk.java.net  Wed Dec  8 07:32:32 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Wed, 8 Dec 2021 07:32:32 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <CFh_IUtVbBOn2iwXKShz_7jLfaHS0OZ3u9zcVz90TZc=.d6458d2e-7809-4493-9df8-8898addd7fb4@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
 <Id0jYVmEcM-5eUkU_AqI_nq9v6_VHK5z-I5regDFgCs=.747a91bf-e04c-4b32-8d11-ecd7913fd035@github.com>
 <CFh_IUtVbBOn2iwXKShz_7jLfaHS0OZ3u9zcVz90TZc=.d6458d2e-7809-4493-9df8-8898addd7fb4@github.com>
Message-ID: <FCSyPTObOj5U1TwDAjIEL3eH1bNm-EdNBgz8ZsJiVPk=.0ba4ad4b-45a4-437e-9b29-e717fda2e431@github.com>

On Tue, 7 Dec 2021 09:24:22 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> > > About the _nc postfix of some of Assembler instructions: we know a bunch of places should be reserved for patching, where we cannot change them into compressed instructions. _nc is short for not compressible - with this, those instructions should keep their origin 4-byte form and remain uncompressed.
> >
> >
> > Why the compressed instructions can not be patched?
>
> Thank you for your reviews, yadong. For example, if we need to relocate oops to another place, we may emit a `movptr`, whose length is fixed, including `lui+addi+slli+addi+slli+addi`. For instructions like `addi`s, if we compress them to a 16-byte form, we will face troubles when we want to relocate them to another place since the new address may not be presented by simple `c.addi`s -- because `c.addi` could only present [-32, +31] but `addi` could present [-2048, +2047]. With this respect, it may be a good choice to remain their original forms for the patchable places, though quite conservative.

The solution by this PR is hooking the assembler and making all instructions as compressed as possible except 'patchable' instructions, because we must make enough room of immutable constants embedded. Let us call it a "**block**" list solution. I don't think there's a proper way to ensure the list is complete, and if incomplete, the result may be a wierd exception/crash or unexpected behavior, and it will be difficult to review and debug.
How about we make a "**white**" list to compressed instruction generation. You can make a compressed region where you think it's safe to do so?for example:


{
CompressRegion cr;
__ addi(rd, rd, 1);
}

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24


From fyang at openjdk.java.net  Wed Dec  8 01:44:45 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Wed, 8 Dec 2021 01:44:45 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
Message-ID: <CqL4H6NLNEl_h-OK8_t3DNdAhtcNoQtCbL8ZOxZE3FI=.6c1e6db7-88b8-443c-85f1-7f35d944e5f3@github.com>

On Tue, 7 Dec 2021 04:46:10 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
>
> This patch support RISC-V RVC extension. It can introduce:
> * 21% code size reduction in template interpreter generated code
> * 20%~25% code size reduction in C1 generated code, evaluated by a common SpringBoot program
> * 15%~20% code size reduction in C2 generated code, evaluated by a common SpringBoot program
>
> In my observation, the code size footprint could be reduced to nearly a level of the AArch64 back-end. About the performance, there seems a stable ~0.7% performance improvement on SPECjbb2015 on one HiFive Unleashed board, considering the code density increase. I think the performance aspect might be a speculative behavior on different hardware implementations because C910's performance might be better than that, but HiFive Unleashed may be more general.
>
> Things about this patch:
> * If an instruction is compressible, then we will implicitly emit a 16-bit compressed instruction instead of the 32-bit instruction in Assembler.
> * About the `_nc` postfix of some of Assembler instructions: we know a bunch of places should be reserved for patching, where we cannot change them into compressed instructions. `_nc` is short for `not compressible` - with this, those instructions should keep their origin 4-byte form and remain uncompressed.
> * There are things not easy to compress like MachBranchNodes. Please see the comments in the code - currently this patch does not support this. We will support this improvement in patches coming afterward.
>
> The macros after their expansion might be like:
>
> void andr(Register Rd, Register Rs1, Register Rs2) {
> +  {
> +    Register src = noreg;
> +    if (UseRVC && Rs1->is_compressed_valid() && Rs2->is_compressed_valid() &&
> +        ((src = Rs1, Rs2 == Rd) || (src = Rs2, Rs1 == Rd))) {
> +      and_c(Rd, src);
> +      return;
> +    }
> +  }
>   unsigned insn = 0;
>   patch((address)&insn, 6, 0, 0b0110011);
>   patch((address)&insn, 14, 12, 0b111);
>   patch((address)&insn, 31, 25, 0b0000000);
>   patch_reg((address)&insn, 7, Rd);
>   patch_reg((address)&insn, 15, Rs1);
>   patch_reg((address)&insn, 20, Rs2);
>   emit(insn);
> };
>
>
> For further information, please see comments in `assembler_riscv_cext.hpp`.
>
> --
>
> This patch may need some time to acquire a review. I have been polishing this patch for quite a long time and it might seem stable under a bunch of full-tier tests and some tier1 jdk/hotspot jtreg tests. But I think we might mark it `experimental` at first, though it is turned on by default. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/7), just for reference, might be quite different from the current one.
>
> I am pleased to receive any suggestion.
>
> Thanks,
> Xiaolin

Well, I don't think it's a good idea for assembler to emit 16-bit compressed instructions by default.
It's quite error prone and will make the code base hard to maintain.
I would suggest the opposite way, i.e., default to 32-bit normal instructions and use compressed instructions when it is absolutly safe.
I see some places where we could make use of compressed instructions.
One scenario would be C2 architecture description file. (C1 should be similar in theory)

Let's say,
6305 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6306   match(Set dst (AddI src1 src2));
6307
6308   ins_cost(ALU_COST);
6309   format %{ "addw  $dst, $src1, $src2\t#@addI_reg_reg" %}
6310
6311   ins_encode %{
6312     __ addw(as_Register($dst$$reg),
6313             as_Register($src1$$reg),
6314             as_Register($src2$$reg));
6315   %}
6316
6317   ins_pipe(ialu_reg_reg);
6318 %}

In this case, I think it should be safe to emit a compressed C.ADD when possible here for this instruct.
Then I think the "addw" assembler function would need one extra argument, say "compress", defaulting to false.
Then for the above instruct, we would call "addw" passing UseRVC as the "compress" argument.
We can then carry out the work incrementally if we go this way and this thus will also make code review easier.
I agree that we will miss some opportunities compared with the current solution, but that shouldn't be a big issue for now.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24


From duke at openjdk.java.net  Thu Dec  9 12:33:17 2021
From: duke at openjdk.java.net (kuaiwei)
Date: Thu, 9 Dec 2021 12:33:17 GMT
Subject: [riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine
 flags register in C2 [v2]
In-Reply-To: <NYCs-AwPo-WWnhgbPvf0m8GnPEpGLAkI2V54RaZx6Sc=.7842f548-1d1e-411c-80ca-2e9c8e926179@github.com>
References: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>
 <6nmr2Yh797p1XjsyRDfGIqp6WfDbJk-o1dR6mTuxbQk=.d1f741ba-bda9-4228-8cb0-43d0e23b0f32@github.com>
 <clf6RXAH1eKel5xuzPlnYNYY-crr8LbfRCJ2d4q21eA=.4d6582c6-827c-4a71-b293-9aa46dd08d16@github.com>
 <ckHHdu6sKy28jRIyAOSvFXdhEnr_J1ybEL6g5cHPNas=.be509b04-c1af-4fe7-baf6-e62d258e5af6@github.com>
 <NYCs-AwPo-WWnhgbPvf0m8GnPEpGLAkI2V54RaZx6Sc=.7842f548-1d1e-411c-80ca-2e9c8e926179@github.com>
Message-ID: <WStMCMmXuuVrZF_nR_Hn9etrpVD5wS3rGMU4lJx0P9A=.f880f2d3-0cf8-4686-bb91-4dd931c4f487@github.com>

On Thu, 2 Dec 2021 13:04:06 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> > > Hi Yadong, it looks cost too much to reserve a dedicated register for control flag. I think in most cases we can use the 2 scratch registers instead. Can you show some complicated cases? We can check if they can be rewrite to avoid the complication.
> >
> >
> > Well, I think there might be some tradeoff here. On the one hand, use the same register 't1' for two different purposes (scratch register & flags registers) at the same time looks rather error prone as mentioned in the PR description. On the other hand, use another register 't2' as the dedicated flags register could somehow affect the performance in certain cases even though this is not reflected on the specjbb2015 numbers. Personally, I have no obvious bias here. I would like to hear how the other Reviewers would say about this. Maybe @shipilev ? Thanks.
>
> Agree. it's a tradeoff. There may be more spill/unspills in some scenarios of a high register pressue, but it is more friendly for code scheduling and higher maintainability with less data flow effects. By the way, we found this PR did not affect the performance of SPECjvm2008 on unmatched:
>
> before?
>
> ```
> compress                      17.71
> crypto                        24.16
> derby                         32.39
> mpegaudio                     14.68
> scimark.large                 3.65
> scimark.small                 15.07
> serial                        12.08
> startup                       3.88
> sunflow                       7.21
> ```
>
> after:
>
> ```
> compress                      17.74
> crypto                        24.1
> derby                         32.67
> mpegaudio                     14.64
> scimark.large                 3.67
> scimark.small                 15.42
> serial                        12.98
> startup                       3.6
> sunflow                       7.09
> ```

Hi Yadong,
Thanks for the test. Since benchmark score showed little impact so far. I'm fine to use a dedicated register now. But it still looks too many special registers in riscv. I think it can be improved in future.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/21


From xlinzheng at openjdk.java.net  Thu Dec  9 06:14:28 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Thu, 9 Dec 2021 06:14:28 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <4To71m1jS-vP-OLwWS3zOg3l_HWxoz1An_mv071UrlA=.3516037c-cc03-4fcd-badf-9b326635ffca@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
 <yqM8SRigjZfjjBoYVXDGtkDE2lqOECMoy86RMYEoe9k=.8456d733-5049-4f32-8aab-90fa08c667e0@github.com>
 <4To71m1jS-vP-OLwWS3zOg3l_HWxoz1An_mv071UrlA=.3516037c-cc03-4fcd-badf-9b326635ffca@github.com>
Message-ID: <QVWVIb1l7rM_PNWptV1sXJoX3O6HEny6xP1hQkAgThk=.ddfeb346-324c-406b-bf57-f2792c901e70@github.com>

On Thu, 9 Dec 2021 05:00:49 GMT, Fei Yang <fyang at openjdk.org> wrote:

> > ### About our first scheme:
> > We may mark some instructions as compressible by adding function arguments. But compressed instructions can be used in almost every place in the code cache, like C1, C2, interpreter, and stub code. The range is quite big -- for instance, after some time we may want to compress some intrinsics, say, `C2_MacroAssembler::string_indexof_char_short()`.
> > After `addi(Rd, Rs, imm)` becomes `addi(Rd, Rs, imm, bool compressible)`, it will be
> > ```
> > bind(MATCH1);
> > addi(index, index, 1);   ->    addi(index, index, 1, true);
> > j(MATCH);                ->    j(MATCH, true);
> >
> > bind(MATCH2);
> > addi(index, index, 2);   ->    addi(index, index, 2, true);
> > j(MATCH);                ->    j(MATCH, true)
> >
> > bind(MATCH3);
> > addi(index, index, 3);   ->   ...
> > j(MATCH);
> >
> > bind(MATCH4);
> > addi(index, index, 4);
> > j(MATCH);
> >
> > bind(MATCH5);
> > addi(index, index, 5);
> > j(MATCH);
> > ```
>
> That's exactly what I mean :-) And this could be carried out incrementally, module by module.
>
> > We might not add extra explicit arguments to them since this may make maintenance quite hard. :-)
>
> No. Passing one extra argument here won't affect future code maintainance in anyway here. In fact, I think this will make reviewer/maintainer's life easier since this makes it explict the places where it's safe to do compress.

Thanks for your quick response, Felix. In fact, I could not realize the philosophy inside this strategy -- so just one double-check: after this, if we define `#define COMPRESSIBLE true` here, I think nearly all the RISC-V backend will be full of `inst(Rd, Rs, ..., COMPRESSIBLE)` everywhere, which means the whole backend's code will be fully coupling with a single RISC-V extension. Hmm... it seems quite unacceptable in my opinion -- could you please simply explain it further for me?

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24


From fyang at openjdk.java.net  Thu Dec  9 06:41:22 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Thu, 9 Dec 2021 06:41:22 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <QVWVIb1l7rM_PNWptV1sXJoX3O6HEny6xP1hQkAgThk=.ddfeb346-324c-406b-bf57-f2792c901e70@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
 <yqM8SRigjZfjjBoYVXDGtkDE2lqOECMoy86RMYEoe9k=.8456d733-5049-4f32-8aab-90fa08c667e0@github.com>
 <4To71m1jS-vP-OLwWS3zOg3l_HWxoz1An_mv071UrlA=.3516037c-cc03-4fcd-badf-9b326635ffca@github.com>
 <QVWVIb1l7rM_PNWptV1sXJoX3O6HEny6xP1hQkAgThk=.ddfeb346-324c-406b-bf57-f2792c901e70@github.com>
Message-ID: <ngzUCm4VgSfj2kDVNZexwIpQ1gG9s7KPvF1SRVZpjmU=.18784e74-9d3f-4ddf-a848-c1272869d4b8@github.com>

On Thu, 9 Dec 2021 06:11:15 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> > > ### About our first scheme:
> > > We may mark some instructions as compressible by adding function arguments. But compressed instructions can be used in almost every place in the code cache, like C1, C2, interpreter, and stub code. The range is quite big -- for instance, after some time we may want to compress some intrinsics, say, `C2_MacroAssembler::string_indexof_char_short()`.
> > > After `addi(Rd, Rs, imm)` becomes `addi(Rd, Rs, imm, bool compressible)`, it will be
> > > ```
> > > bind(MATCH1);
> > > addi(index, index, 1);   ->    addi(index, index, 1, true);
> > > j(MATCH);                ->    j(MATCH, true);
> > >
> > > bind(MATCH2);
> > > addi(index, index, 2);   ->    addi(index, index, 2, true);
> > > j(MATCH);                ->    j(MATCH, true)
> > >
> > > bind(MATCH3);
> > > addi(index, index, 3);   ->   ...
> > > j(MATCH);
> > >
> > > bind(MATCH4);
> > > addi(index, index, 4);
> > > j(MATCH);
> > >
> > > bind(MATCH5);
> > > addi(index, index, 5);
> > > j(MATCH);
> > > ```
> >
> >
> > That's exactly what I mean :-) And this could be carried out incrementally, module by module.
> > > We might not add extra explicit arguments to them since this may make maintenance quite hard. :-)
> >
> >
> > No. Passing one extra argument here won't affect future code maintainance in anyway here. In fact, I think this will make reviewer/maintainer's life easier since this makes it explict the places where it's safe to do compress.
>
> Thanks for your quick response, Felix. In fact, I could not realize the philosophy inside this strategy -- so just one double-check: after this, if we define `#define COMPRESSIBLE true` here, I think nearly all the RISC-V backend will be full of `inst(Rd, Rs, ..., COMPRESSIBLE)` everywhere, which means the whole backend's code will be fully coupling with a single RISC-V extension. Hmm... it seems quite unacceptable in my opinion -- could you please simply explain it further for me?

In fact, I am not expecting we catch all the possible places in the backend converting to compressed instructions.
I guess maybe the best places to do this would be C1 and C2.
It doesn't make much sense to me to do this kind of thing for code stubs, template interpreter, runtime, etc.
We might churn too much without little gain.
Code size might be an issue for 32-bit RV32G embedded systems, but I feel it's less likely an big issue for 64-bit systems like RV64G. I even doubt future chip vendors would ship this RVC feature for RV64G systems.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24


From fyang at openjdk.java.net  Thu Dec  9 07:45:23 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Thu, 9 Dec 2021 07:45:23 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
Message-ID: <H0tgM8Vs-y8pA0uUDAvfkTaUOcyVaFrusLomwKLGYBE=.348537cd-2dba-4d93-ba78-1172891a3b0f@github.com>

On Tue, 7 Dec 2021 04:46:10 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
>
> This patch support RISC-V RVC extension. It can introduce:
> * 21% code size reduction in template interpreter generated code
> * 20%~25% code size reduction in C1 generated code, evaluated by a common SpringBoot program
> * 15%~20% code size reduction in C2 generated code, evaluated by a common SpringBoot program
>
> In my observation, the code size footprint could be reduced to nearly a level of the AArch64 back-end. About the performance, there seems a stable ~0.7% performance improvement on SPECjbb2015 on one HiFive Unleashed board, considering the code density increase. I think the performance aspect might be a speculative behavior on different hardware implementations because C910's performance might be better than that, but HiFive Unleashed may be more general.
>
> Things about this patch:
> * If an instruction is compressible, then we will implicitly emit a 16-bit compressed instruction instead of the 32-bit instruction in Assembler.
> * About the `_nc` postfix of some of Assembler instructions: we know a bunch of places should be reserved for patching, where we cannot change them into compressed instructions. `_nc` is short for `not compressible` - with this, those instructions should keep their origin 4-byte form and remain uncompressed.
> * There are things not easy to compress like MachBranchNodes. Please see the comments in the code - currently this patch does not support this. We will support this improvement in patches coming afterward.
>
> The macros after their expansion might be like:
>
> void andr(Register Rd, Register Rs1, Register Rs2) {
> +  {
> +    Register src = noreg;
> +    if (UseRVC && Rs1->is_compressed_valid() && Rs2->is_compressed_valid() &&
> +        ((src = Rs1, Rs2 == Rd) || (src = Rs2, Rs1 == Rd))) {
> +      and_c(Rd, src);
> +      return;
> +    }
> +  }
>   unsigned insn = 0;
>   patch((address)&insn, 6, 0, 0b0110011);
>   patch((address)&insn, 14, 12, 0b111);
>   patch((address)&insn, 31, 25, 0b0000000);
>   patch_reg((address)&insn, 7, Rd);
>   patch_reg((address)&insn, 15, Rs1);
>   patch_reg((address)&insn, 20, Rs2);
>   emit(insn);
> };
>
>
> For further information, please see comments in `assembler_riscv_cext.hpp`.
>
> --
>
> This patch may need some time to acquire a review. I have been polishing this patch for quite a long time and it might seem stable under a bunch of full-tier tests and some tier1 jdk/hotspot jtreg tests. But I think we might mark it `experimental` at first, though it is turned on by default. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/7), just for reference, might be quite different from the current one.
>
> I am pleased to receive any suggestion.
>
> Thanks,
> Xiaolin

Based on my last comment, I think we can then further consider the "CompressibleRegion" solution suggested by Yadong.
That way we will avoid adding the COMPRESSIBLE argument in many places. Just leave aside the uncertain places.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24


From fyang at openjdk.java.net  Thu Dec  9 11:51:15 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Thu, 9 Dec 2021 11:51:15 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <aQ89BeSyJbFv54Zizt_biN1AvNeGYaUjCFa_A3pT_Tg=.6656d726-337d-4e17-b51e-c1880472cdf7@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
 <aQ89BeSyJbFv54Zizt_biN1AvNeGYaUjCFa_A3pT_Tg=.6656d726-337d-4e17-b51e-c1880472cdf7@github.com>
Message-ID: <_00TOqP90Pr2PP_ZJSJBfwmRvgZKsW_rbg_iTLIBFpM=.3f0c5636-a4cd-4569-b41c-c90dee141e1d@github.com>

On Thu, 9 Dec 2021 09:39:06 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Thank you for your explanation, Felix. :-) Seems we finally reach a consensus now.
>
> > I guess maybe the best places to do this would be C1 and C2.
>
> I think I could get your meaning this time.
>
> > I think we can then further consider the "CompressibleRegion" solution suggested by Yadong.
>
> Yadong's plan works for me. I am quite in favor of his strategy.

I am happy that we are agreed on this solution ;-)
We need to be safe at this very early stage, so I would suggest UseRVC disabled by default like UseRVV even if the hardware RVC extension is there. I hope you could understand that.
In the future, we will consider auto-enable UseRVC and UseRVV after enough testing and evaluation.

> I will implement this approach ASAP. Maybe next week I might open another PR including this implementation and the definition of compressed instructions presented in the `assembler_riscv_cext.hpp` part for a better review. I wonder if this is okay for you.
>
> I am going to close this PR, save it for future reference, and may open another PR and start from scratch. Before that, just one more question: would you mind my keeping definitions of C-Ext instructions into one separate file like `assembler_riscv_cext.hpp`, as the current implementation? I think we might better keep different RISCV extensions into different files.

Yes, I think `assembler_riscv_c.hpp` will do here.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24


From xlinzheng at openjdk.java.net  Thu Dec  9 11:58:21 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Thu, 9 Dec 2021 11:58:21 GMT
Subject: [riscv-port] Withdrawn: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
Message-ID: <wiTHI8QXxuWE_CazwmonfT49Dl_x2v6IKcQS8Xy6BTY=.3c69418d-824d-4f4e-9649-6066b5a4cad2@github.com>

On Tue, 7 Dec 2021 04:46:10 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
>
> This patch support RISC-V RVC extension. It can introduce:
> * 21% code size reduction in template interpreter generated code
> * 20%~25% code size reduction in C1 generated code, evaluated by a common SpringBoot program
> * 15%~20% code size reduction in C2 generated code, evaluated by a common SpringBoot program
>
> In my observation, the code size footprint could be reduced to nearly a level of the AArch64 back-end. About the performance, there seems a stable ~0.7% performance improvement on SPECjbb2015 on one HiFive Unleashed board, considering the code density increase. I think the performance aspect might be a speculative behavior on different hardware implementations because C910's performance might be better than that, but HiFive Unleashed may be more general.
>
> Things about this patch:
> * If an instruction is compressible, then we will implicitly emit a 16-bit compressed instruction instead of the 32-bit instruction in Assembler.
> * About the `_nc` postfix of some of Assembler instructions: we know a bunch of places should be reserved for patching, where we cannot change them into compressed instructions. `_nc` is short for `not compressible` - with this, those instructions should keep their origin 4-byte form and remain uncompressed.
> * There are things not easy to compress like MachBranchNodes. Please see the comments in the code - currently this patch does not support this. We will support this improvement in patches coming afterward.
>
> The macros after their expansion might be like:
>
> void andr(Register Rd, Register Rs1, Register Rs2) {
> +  {
> +    Register src = noreg;
> +    if (UseRVC && Rs1->is_compressed_valid() && Rs2->is_compressed_valid() &&
> +        ((src = Rs1, Rs2 == Rd) || (src = Rs2, Rs1 == Rd))) {
> +      and_c(Rd, src);
> +      return;
> +    }
> +  }
>   unsigned insn = 0;
>   patch((address)&insn, 6, 0, 0b0110011);
>   patch((address)&insn, 14, 12, 0b111);
>   patch((address)&insn, 31, 25, 0b0000000);
>   patch_reg((address)&insn, 7, Rd);
>   patch_reg((address)&insn, 15, Rs1);
>   patch_reg((address)&insn, 20, Rs2);
>   emit(insn);
> };
>
>
> For further information, please see comments in `assembler_riscv_cext.hpp`.
>
> --
>
> This patch may need some time to acquire a review. I have been polishing this patch for quite a long time and it might seem stable under a bunch of full-tier tests and some tier1 jdk/hotspot jtreg tests. But I think we might mark it `experimental` at first, though it is turned on by default. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/7), just for reference, might be quite different from the current one.
>
> I am pleased to receive any suggestion.
>
> Thanks,
> Xiaolin

This pull request has been closed without being integrated.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24


From xlinzheng at openjdk.java.net  Thu Dec  9 09:42:25 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Thu, 9 Dec 2021 09:42:25 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
Message-ID: <aQ89BeSyJbFv54Zizt_biN1AvNeGYaUjCFa_A3pT_Tg=.6656d726-337d-4e17-b51e-c1880472cdf7@github.com>

On Tue, 7 Dec 2021 04:46:10 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
>
> This patch support RISC-V RVC extension. It can introduce:
> * 21% code size reduction in template interpreter generated code
> * 20%~25% code size reduction in C1 generated code, evaluated by a common SpringBoot program
> * 15%~20% code size reduction in C2 generated code, evaluated by a common SpringBoot program
>
> In my observation, the code size footprint could be reduced to nearly a level of the AArch64 back-end. About the performance, there seems a stable ~0.7% performance improvement on SPECjbb2015 on one HiFive Unleashed board, considering the code density increase. I think the performance aspect might be a speculative behavior on different hardware implementations because C910's performance might be better than that, but HiFive Unleashed may be more general.
>
> Things about this patch:
> * If an instruction is compressible, then we will implicitly emit a 16-bit compressed instruction instead of the 32-bit instruction in Assembler.
> * About the `_nc` postfix of some of Assembler instructions: we know a bunch of places should be reserved for patching, where we cannot change them into compressed instructions. `_nc` is short for `not compressible` - with this, those instructions should keep their origin 4-byte form and remain uncompressed.
> * There are things not easy to compress like MachBranchNodes. Please see the comments in the code - currently this patch does not support this. We will support this improvement in patches coming afterward.
>
> The macros after their expansion might be like:
>
> void andr(Register Rd, Register Rs1, Register Rs2) {
> +  {
> +    Register src = noreg;
> +    if (UseRVC && Rs1->is_compressed_valid() && Rs2->is_compressed_valid() &&
> +        ((src = Rs1, Rs2 == Rd) || (src = Rs2, Rs1 == Rd))) {
> +      and_c(Rd, src);
> +      return;
> +    }
> +  }
>   unsigned insn = 0;
>   patch((address)&insn, 6, 0, 0b0110011);
>   patch((address)&insn, 14, 12, 0b111);
>   patch((address)&insn, 31, 25, 0b0000000);
>   patch_reg((address)&insn, 7, Rd);
>   patch_reg((address)&insn, 15, Rs1);
>   patch_reg((address)&insn, 20, Rs2);
>   emit(insn);
> };
>
>
> For further information, please see comments in `assembler_riscv_cext.hpp`.
>
> --
>
> This patch may need some time to acquire a review. I have been polishing this patch for quite a long time and it might seem stable under a bunch of full-tier tests and some tier1 jdk/hotspot jtreg tests. But I think we might mark it `experimental` at first, though it is turned on by default. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/7), just for reference, might be quite different from the current one.
>
> I am pleased to receive any suggestion.
>
> Thanks,
> Xiaolin

Thank you for your explanation, Felix. :-) Seems we finally reach a consensus now.

> I guess maybe the best places to do this would be C1 and C2.

I think I could get your meaning this time.

> I think we can then further consider the "CompressibleRegion" solution suggested by Yadong.

Yadong's plan works for me. I am quite in favor of his strategy.

I will implement this approach ASAP. Maybe next week I might open another PR including this implementation and the definition of compressed instructions presented in the `assembler_riscv_cext.hpp` part for a better review. I wonder if this is okay for you.

I am going to close this PR, save it for future reference, and may open another PR and start from scratch. Before that, just one more question: would you mind my keeping definitions of C-Ext instructions into one separate file like `assembler_riscv_cext.hpp`, as the current implementation? I think we might better keep different RISCV extensions into different files.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24


From xlinzheng at openjdk.java.net  Thu Dec  9 11:58:20 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Thu, 9 Dec 2021 11:58:20 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <_00TOqP90Pr2PP_ZJSJBfwmRvgZKsW_rbg_iTLIBFpM=.3f0c5636-a4cd-4569-b41c-c90dee141e1d@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
 <aQ89BeSyJbFv54Zizt_biN1AvNeGYaUjCFa_A3pT_Tg=.6656d726-337d-4e17-b51e-c1880472cdf7@github.com>
 <_00TOqP90Pr2PP_ZJSJBfwmRvgZKsW_rbg_iTLIBFpM=.3f0c5636-a4cd-4569-b41c-c90dee141e1d@github.com>
Message-ID: <tgS3OlAhZLwOEhbq6Xpd0cbdU0ffchNMFuhDQpFfDk0=.5002d6d0-ffb1-47f3-89bc-dbc78b470aa4@github.com>

On Thu, 9 Dec 2021 11:47:51 GMT, Fei Yang <fyang at openjdk.org> wrote:

> > Thank you for your explanation, Felix. :-) Seems we finally reach a consensus now.
> > > I guess maybe the best places to do this would be C1 and C2.
> >
> >
> > I think I could get your meaning this time.
> > > I think we can then further consider the "CompressibleRegion" solution suggested by Yadong.
> >
> >
> > Yadong's plan works for me. I am quite in favor of his strategy.
>
> I am happy that we are agreed on this solution ;-) We need to be safe at this very early stage, so I would suggest UseRVC disabled by default like UseRVV even if the hardware RVC extension is there. I hope you could understand that. In the future, we will consider auto-enable UseRVC and UseRVV after enough testing and evaluation.
>
> > I will implement this approach ASAP. Maybe next week I might open another PR including this implementation and the definition of compressed instructions presented in the `assembler_riscv_cext.hpp` part for a better review. I wonder if this is okay for you.
> > I am going to close this PR, save it for future reference, and may open another PR and start from scratch. Before that, just one more question: would you mind my keeping definitions of C-Ext instructions into one separate file like `assembler_riscv_cext.hpp`, as the current implementation? I think we might better keep different RISCV extensions into different files.
>
> Yes, I think `assembler_riscv_c.hpp` will do here.

Totally agree --
Thanks again for your reviews.
Gonna close this PR and the related issue.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24


From yadongwang at openjdk.java.net  Thu Dec  9 13:55:29 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Thu, 9 Dec 2021 13:55:29 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <tgS3OlAhZLwOEhbq6Xpd0cbdU0ffchNMFuhDQpFfDk0=.5002d6d0-ffb1-47f3-89bc-dbc78b470aa4@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
 <aQ89BeSyJbFv54Zizt_biN1AvNeGYaUjCFa_A3pT_Tg=.6656d726-337d-4e17-b51e-c1880472cdf7@github.com>
 <_00TOqP90Pr2PP_ZJSJBfwmRvgZKsW_rbg_iTLIBFpM=.3f0c5636-a4cd-4569-b41c-c90dee141e1d@github.com>
 <tgS3OlAhZLwOEhbq6Xpd0cbdU0ffchNMFuhDQpFfDk0=.5002d6d0-ffb1-47f3-89bc-dbc78b470aa4@github.com>
Message-ID: <YnuZYRCdSUwh8Gg-nbA5wCEYXdTaX1kVWwWzhZqgloQ=.9792e904-ed11-48a0-bb77-c974aeb2ef46@github.com>

On Thu, 9 Dec 2021 11:55:37 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> > > Thank you for your explanation, Felix. :-) Seems we finally reach a consensus now.
> > > > I guess maybe the best places to do this would be C1 and C2.
> > >
> > >
> > > I think I could get your meaning this time.
> > > > I think we can then further consider the "CompressibleRegion" solution suggested by Yadong.
> > >
> > >
> > > Yadong's plan works for me. I am quite in favor of his strategy.
> >
> >
> > I am happy that we are agreed on this solution ;-) We need to be safe at this very early stage, so I would suggest UseRVC disabled by default like UseRVV even if the hardware RVC extension is there. I hope you could understand that. In the future, we will consider auto-enable UseRVC and UseRVV after enough testing and evaluation.
> > > I will implement this approach ASAP. Maybe next week I might open another PR including this implementation and the definition of compressed instructions presented in the `assembler_riscv_cext.hpp` part for a better review. I wonder if this is okay for you.
> > > I am going to close this PR, save it for future reference, and may open another PR and start from scratch. Before that, just one more question: would you mind my keeping definitions of C-Ext instructions into one separate file like `assembler_riscv_cext.hpp`, as the current implementation? I think we might better keep different RISCV extensions into different files.
> >
> >
> > Yes, I think `assembler_riscv_c.hpp` will do here.
>
> Totally agree -- Thanks again for your reviews. Gonna close this PR and the related issue.

@zhengxiaolinX I think a seperate file for rvc is a good choice, and maybe we should do the same thing for rvv later.
By the way, the Open/Closed principle may be suitable for your design. We can use a RVC_Assembler extend the Assembler, override all instructions that may be compressed, and then deliver to the super Assembler if the "compression" failed. Maybe you can swap the context easier when entering or leaving the "CompressedRegion". Just for suggestion, and thank you for your big effort.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24


From xlinzheng at openjdk.java.net  Thu Dec  9 14:23:35 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Thu, 9 Dec 2021 14:23:35 GMT
Subject: [riscv-port] RFR: 8278322: riscv: Support RVC: compressed
 instructions
In-Reply-To: <YnuZYRCdSUwh8Gg-nbA5wCEYXdTaX1kVWwWzhZqgloQ=.9792e904-ed11-48a0-bb77-c974aeb2ef46@github.com>
References: <eQfl_hMsSijCTxCF97x74sqJDNuFqEUBQspExaE--9U=.2ca413f2-5322-45f7-a6fd-24a7e739f4c6@github.com>
 <aQ89BeSyJbFv54Zizt_biN1AvNeGYaUjCFa_A3pT_Tg=.6656d726-337d-4e17-b51e-c1880472cdf7@github.com>
 <_00TOqP90Pr2PP_ZJSJBfwmRvgZKsW_rbg_iTLIBFpM=.3f0c5636-a4cd-4569-b41c-c90dee141e1d@github.com>
 <tgS3OlAhZLwOEhbq6Xpd0cbdU0ffchNMFuhDQpFfDk0=.5002d6d0-ffb1-47f3-89bc-dbc78b470aa4@github.com>
 <YnuZYRCdSUwh8Gg-nbA5wCEYXdTaX1kVWwWzhZqgloQ=.9792e904-ed11-48a0-bb77-c974aeb2ef46@github.com>
Message-ID: <j56o3wZEhFvqE96mL6z6R8f93Zdgmjj-5GIpxqdPJno=.f4e1989b-72a9-4589-86f9-e5fa44078160@github.com>

On Thu, 9 Dec 2021 13:51:41 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> > > > Thank you for your explanation, Felix. :-) Seems we finally reach a consensus now.
> > > > > I guess maybe the best places to do this would be C1 and C2.
> > > >
> > > >
> > > > I think I could get your meaning this time.
> > > > > I think we can then further consider the "CompressibleRegion" solution suggested by Yadong.
> > > >
> > > >
> > > > Yadong's plan works for me. I am quite in favor of his strategy.
> > >
> > >
> > > I am happy that we are agreed on this solution ;-) We need to be safe at this very early stage, so I would suggest UseRVC disabled by default like UseRVV even if the hardware RVC extension is there. I hope you could understand that. In the future, we will consider auto-enable UseRVC and UseRVV after enough testing and evaluation.
> > > > I will implement this approach ASAP. Maybe next week I might open another PR including this implementation and the definition of compressed instructions presented in the `assembler_riscv_cext.hpp` part for a better review. I wonder if this is okay for you.
> > > > I am going to close this PR, save it for future reference, and may open another PR and start from scratch. Before that, just one more question: would you mind my keeping definitions of C-Ext instructions into one separate file like `assembler_riscv_cext.hpp`, as the current implementation? I think we might better keep different RISCV extensions into different files.
> > >
> > >
> > > Yes, I think `assembler_riscv_c.hpp` will do here.
> >
> >
> > Totally agree -- Thanks again for your reviews. Gonna close this PR and the related issue.
>
> @zhengxiaolinX I think a seperate file for rvc is a good choice, and maybe we should do the same thing for rvv later. By the way, the Open/Closed principle may be suitable for your design. We can use a RVC_Assembler extend the Assembler, override all instructions that may be compressed, and then deliver to the super Assembler if the "compression" failed. Maybe you can swap the context easier when entering or leaving the "CompressedRegion". Just for suggestion, and thank you for your big effort.

Thanks for you suggestion, Yadong. In fact I nearly have the same consideration about this. RISC-V is a modularized ISA with pluggable extensions. Now that extensions will be supported one by one, I think the codebase will inevitably full of lots of unreadable `if (A-Ext enabed)...else...  if (B-Ext enabled)...else...` unified in one VM in order to handle all possible cases. The runtime costs of performance will graduately get bigger and bigger as time goes. So we might do the same modularized things in the Assembler as your words from the beginning to prevent regrets, for at last code might be extremely difficult to get refactored. I have noticed that at every instruction I need to check one `UseRVC` now, but the workload might be so big to change that so I didn't determine if I should do that. After your words, I realize if we are thinking about the same thing, we might start to consider changes from the beginning. Thanks again for your advice and I will take this into a careful co
 nsideration.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/24

From duke at openjdk.java.net  Wed Dec  8 01:21:47 2021
From: duke at openjdk.java.net (kuaiwei)
Date: Wed, 8 Dec 2021 01:21:47 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr
 around calls
In-Reply-To: <KqwS67LHtLTP130isf6iRE3e3T6EIYD9ldTCHBiEz_o=.9893496e-5082-41f1-acd1-48a5ed47931d@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
 <KqwS67LHtLTP130isf6iRE3e3T6EIYD9ldTCHBiEz_o=.9893496e-5082-41f1-acd1-48a5ed47931d@github.com>
Message-ID: <y8pgOz372B9hmOYRwr9Q3VKy6FKpftM7klvthdvFJjA=.e16faf6c-da73-4627-bc1b-a4ba0d9dc7ce@github.com>

On Tue, 7 Dec 2021 12:43:08 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> It seems zr(x0) is used as stack alignment when saving/restoring registers around calls. But it's unnecessary to ld/st x0 from/to stack. We just need reserve a stack slot in case alignment is required.
>
> src/hotspot/cpu/riscv/riscv.ad line 1188:
>
>> 1186:     return 12 * NativeInstruction::instruction_size;
>> 1187:   }
>> 1188: }
>
> `// for real runtime callouts it will be six instructions` should be five instructions now

The 2 la macro instructions will be expand to 8 instructions. In XiaoLin's recent patch, he added detail in comments.

//   la(t1, retaddr)                ->  auipc + addi
//   la(t0, RuntimeAddress(addr))   ->  lui + addi + slli(C) + addi + slli(C) + addi
//   addi(sp, sp, -2 * wordSize)    ->  addi(C)
//   sd(zr, Address(sp))            ->  sd(C)
//   sd(t1, Address(sp, wordSize))  ->  sd(C)
//   jalr(t0)                       ->  jalr(C)

Check https://github.com/openjdk/riscv-port/pull/24/files#diff-e3c18b8b83898e82b5a3069319df6a47468e91cc2527bf065e704a685a20f26b

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/25


From duke at openjdk.java.net  Wed Dec  8 06:43:31 2021
From: duke at openjdk.java.net (kuaiwei)
Date: Wed, 8 Dec 2021 06:43:31 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr
 around calls [v2]
In-Reply-To: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
Message-ID: <EsXYUgWFqFEVM2EtQrpfR6F6CHfzVkoPJFRaPKFkbes=.c995ae05-3dfd-43ed-805c-b98c0ccec8e4@github.com>

> It seems zr(x0) is used as stack alignment when saving/restoring registers around calls. But it's unnecessary to ld/st x0 from/to stack. We just need reserve a stack slot in case alignment is required.

kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision:

8278337: riscv: remove unnecessary ld/sd zr around call

-------------

Changes:
- all: https://git.openjdk.java.net/riscv-port/pull/25/files
- new: https://git.openjdk.java.net/riscv-port/pull/25/files/5f8767ca..ddc32f4e

Webrevs:
- full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=25&range=01
- incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=25&range=00-01

Stats: 1 line in 1 file changed: 0 ins; 0 del; 1 mod
Patch: https://git.openjdk.java.net/riscv-port/pull/25.diff
Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/25/head:pull/25

PR: https://git.openjdk.java.net/riscv-port/pull/25


From fyang at openjdk.java.net  Wed Dec  8 08:45:49 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Wed, 8 Dec 2021 08:45:49 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr
 around calls [v2]
In-Reply-To: <EsXYUgWFqFEVM2EtQrpfR6F6CHfzVkoPJFRaPKFkbes=.c995ae05-3dfd-43ed-805c-b98c0ccec8e4@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
 <EsXYUgWFqFEVM2EtQrpfR6F6CHfzVkoPJFRaPKFkbes=.c995ae05-3dfd-43ed-805c-b98c0ccec8e4@github.com>
Message-ID: <R2BntEFbuX8b85j9LRKPgdGFNulj7_HWDxnd8RUc87c=.a6b99922-2662-4c6a-87da-6023399fb860@github.com>

On Wed, 8 Dec 2021 06:43:31 GMT, kuaiwei <duke at openjdk.java.net> wrote:

>> It seems zr(x0) is used as stack alignment when saving/restoring registers around calls. But it's unnecessary to ld/st x0 from/to stack. We just need reserve a stack slot in case alignment is required.
>
> kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision:
>
>   8278337: riscv: remove unnecessary ld/sd zr around call

May I ask what kind of test is carried out for this change? Normally, testing result should also be added in PR description.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/25


From fyang at openjdk.java.net  Wed Dec  8 08:37:50 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Wed, 8 Dec 2021 08:37:50 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr
 around calls [v2]
In-Reply-To: <EsXYUgWFqFEVM2EtQrpfR6F6CHfzVkoPJFRaPKFkbes=.c995ae05-3dfd-43ed-805c-b98c0ccec8e4@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
 <EsXYUgWFqFEVM2EtQrpfR6F6CHfzVkoPJFRaPKFkbes=.c995ae05-3dfd-43ed-805c-b98c0ccec8e4@github.com>
Message-ID: <4uZKe1g6a2I0eG8I9B2Oep6mZr9l_rVpTXA8pON0YXc=.ad7ce0cc-2dcd-4b46-baf5-3e582ff83cd2@github.com>

On Wed, 8 Dec 2021 06:43:31 GMT, kuaiwei <duke at openjdk.java.net> wrote:

>> It seems zr(x0) is used as stack alignment when saving/restoring registers around calls. But it's unnecessary to ld/st x0 from/to stack. We just need reserve a stack slot in case alignment is required.
>
> kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision:
>
>   8278337: riscv: remove unnecessary ld/sd zr around call

Changes requested by fyang (Lead).

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 958:

> 956:   int count = 0;
> 957:   // Zr and sp (x0, x2) should not be pushed
> 958:   assert((bitset & 0b101) == 0, "zr or sp is in bitset: %x", bitset);

I don't think we need this assertion here. Function bitset_to_regs should not care about specific registers in the set.

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 983:

> 981:   }
> 982:   for (int i = count - 1; i >= 0; i--) {
> 983:     sd(as_Register(regs[i]), Address(stack, (count -1 - i) * wordSize + offset));

whitespace is missing here. Should be: (count - 1 - i)

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/25


From fjiang at openjdk.java.net  Wed Dec  8 07:49:45 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Wed, 8 Dec 2021 07:49:45 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr
 around calls [v2]
In-Reply-To: <MENTTWepPuXGo0MW_BFI6Z3bQO_63bI4iuLimGXK_6o=.7d8670c9-385c-4c26-bca2-e07caf09e090@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
 <KqwS67LHtLTP130isf6iRE3e3T6EIYD9ldTCHBiEz_o=.9893496e-5082-41f1-acd1-48a5ed47931d@github.com>
 <MENTTWepPuXGo0MW_BFI6Z3bQO_63bI4iuLimGXK_6o=.7d8670c9-385c-4c26-bca2-e07caf09e090@github.com>
Message-ID: <PyH3gb4jRQ43KoUws2Em90ZTHs-gUS6fbu6erTzPHFY=.e761a081-4bc2-4e4f-91da-53102b4d0bfa@github.com>

On Wed, 8 Dec 2021 06:31:58 GMT, kuaiwei <duke at openjdk.java.net> wrote:

>> src/hotspot/cpu/riscv/riscv.ad line 1188:
>>
>>> 1186:     return 12 * NativeInstruction::instruction_size;
>>> 1187:   }
>>> 1188: }
>>
>> `// for real runtime callouts it will be six instructions` should be five instructions now
>
> Fixed

Thanks. BTW, you can push another commit after starting the review instead of force pushing.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/25


From duke at openjdk.java.net  Wed Dec  8 06:43:32 2021
From: duke at openjdk.java.net (kuaiwei)
Date: Wed, 8 Dec 2021 06:43:32 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr
 around calls [v2]
In-Reply-To: <KqwS67LHtLTP130isf6iRE3e3T6EIYD9ldTCHBiEz_o=.9893496e-5082-41f1-acd1-48a5ed47931d@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
 <KqwS67LHtLTP130isf6iRE3e3T6EIYD9ldTCHBiEz_o=.9893496e-5082-41f1-acd1-48a5ed47931d@github.com>
Message-ID: <MENTTWepPuXGo0MW_BFI6Z3bQO_63bI4iuLimGXK_6o=.7d8670c9-385c-4c26-bca2-e07caf09e090@github.com>

On Tue, 7 Dec 2021 12:43:08 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision:
>>
>>   8278337: riscv: remove unnecessary ld/sd zr around call
>
> src/hotspot/cpu/riscv/riscv.ad line 1188:
>
>> 1186:     return 12 * NativeInstruction::instruction_size;
>> 1187:   }
>> 1188: }
>
> `// for real runtime callouts it will be six instructions` should be five instructions now

Fixed

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/25


From fyang at openjdk.java.net  Wed Dec  8 08:42:45 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Wed, 8 Dec 2021 08:42:45 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr
 around calls [v2]
In-Reply-To: <PyH3gb4jRQ43KoUws2Em90ZTHs-gUS6fbu6erTzPHFY=.e761a081-4bc2-4e4f-91da-53102b4d0bfa@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
 <KqwS67LHtLTP130isf6iRE3e3T6EIYD9ldTCHBiEz_o=.9893496e-5082-41f1-acd1-48a5ed47931d@github.com>
 <MENTTWepPuXGo0MW_BFI6Z3bQO_63bI4iuLimGXK_6o=.7d8670c9-385c-4c26-bca2-e07caf09e090@github.com>
 <PyH3gb4jRQ43KoUws2Em90ZTHs-gUS6fbu6erTzPHFY=.e761a081-4bc2-4e4f-91da-53102b4d0bfa@github.com>
Message-ID: <YlXOx8QSmv5lP4cQfhmCVcU6joF8XpJCNsxrJgdlYGA=.d71d5510-2b9f-4d3b-bbf1-7b87fe3a9a9e@github.com>

On Wed, 8 Dec 2021 07:45:58 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> Fixed
>
> Thanks. BTW, you can push another commit after starting the review instead of force pushing.

Yes. To modify your patch in a pull request, just push more changes to the branch the pull request is based on.
Reference:
https://wiki.openjdk.java.net/display/SKARA/FAQ#FAQ-HowdoImodifythechangesinapullrequest?

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/25


From duke at openjdk.java.net  Wed Dec  8 12:53:15 2021
From: duke at openjdk.java.net (kuaiwei)
Date: Wed, 8 Dec 2021 12:53:15 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr
 around calls [v2]
In-Reply-To: <EsXYUgWFqFEVM2EtQrpfR6F6CHfzVkoPJFRaPKFkbes=.c995ae05-3dfd-43ed-805c-b98c0ccec8e4@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
 <EsXYUgWFqFEVM2EtQrpfR6F6CHfzVkoPJFRaPKFkbes=.c995ae05-3dfd-43ed-805c-b98c0ccec8e4@github.com>
Message-ID: <IXw6CiHLNItRV1tQrJDDk_u5ImvlP8nU8s-gqS-zrPk=.fc66503c-58a0-406f-ba68-9b2b6984c6e4@github.com>

On Wed, 8 Dec 2021 06:43:31 GMT, kuaiwei <duke at openjdk.java.net> wrote:

>> It seems zr(x0) is used as stack alignment when saving/restoring registers around calls. But it's unnecessary to ld/st x0 from/to stack. We just need reserve a stack slot in case alignment is required.
>
> kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.

>
Hi Felix,  the patch passed tier1 test in qemu with fastdebug build.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/25


From duke at openjdk.java.net  Wed Dec  8 12:53:17 2021
From: duke at openjdk.java.net (kuaiwei)
Date: Wed, 8 Dec 2021 12:53:17 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr
 around calls [v2]
In-Reply-To: <4uZKe1g6a2I0eG8I9B2Oep6mZr9l_rVpTXA8pON0YXc=.ad7ce0cc-2dcd-4b46-baf5-3e582ff83cd2@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
 <EsXYUgWFqFEVM2EtQrpfR6F6CHfzVkoPJFRaPKFkbes=.c995ae05-3dfd-43ed-805c-b98c0ccec8e4@github.com>
 <4uZKe1g6a2I0eG8I9B2Oep6mZr9l_rVpTXA8pON0YXc=.ad7ce0cc-2dcd-4b46-baf5-3e582ff83cd2@github.com>
Message-ID: <4OauBUXECKEzICGiFLaRHjFljBLIAwNcFRCwebVzFuQ=.8ed7337c-eaac-4e30-8589-f3e9bf0a9042@github.com>

On Wed, 8 Dec 2021 08:32:18 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 958:
>
>> 956:   int count = 0;
>> 957:   // Zr and sp (x0, x2) should not be pushed
>> 958:   assert((bitset & 0b101) == 0, "zr or sp is in bitset: %x", bitset);
>
> I don't think we need this assertion here. Function bitset_to_regs should not care about specific registers in the set.

Removed as comment. Thanks.

> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 983:
>
>> 981:   }
>> 982:   for (int i = count - 1; i >= 0; i--) {
>> 983:     sd(as_Register(regs[i]), Address(stack, (count -1 - i) * wordSize + offset));
>
> whitespace is missing here. Should be: (count - 1 - i)

Fixed.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/25


From duke at openjdk.java.net  Wed Dec  8 12:53:17 2021
From: duke at openjdk.java.net (kuaiwei)
Date: Wed, 8 Dec 2021 12:53:17 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr
 around calls [v3]
In-Reply-To: <YlXOx8QSmv5lP4cQfhmCVcU6joF8XpJCNsxrJgdlYGA=.d71d5510-2b9f-4d3b-bbf1-7b87fe3a9a9e@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
 <KqwS67LHtLTP130isf6iRE3e3T6EIYD9ldTCHBiEz_o=.9893496e-5082-41f1-acd1-48a5ed47931d@github.com>
 <MENTTWepPuXGo0MW_BFI6Z3bQO_63bI4iuLimGXK_6o=.7d8670c9-385c-4c26-bca2-e07caf09e090@github.com>
 <PyH3gb4jRQ43KoUws2Em90ZTHs-gUS6fbu6erTzPHFY=.e761a081-4bc2-4e4f-91da-53102b4d0bfa@github.com>
 <YlXOx8QSmv5lP4cQfhmCVcU6joF8XpJCNsxrJgdlYGA=.d71d5510-2b9f-4d3b-bbf1-7b87fe3a9a9e@github.com>
Message-ID: <s9Zx21jbfbHRvI97LPcHpQmEaACr2U8icYhE09deymA=.ef7da2bb-fbe3-4ae9-a4c3-eb97101ada95@github.com>

On Wed, 8 Dec 2021 08:39:45 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Thanks. BTW, you can push another commit after starting the review instead of force pushing.
>
> Yes. To modify your patch in a pull request, just push more changes to the branch the pull request is based on.
> Reference:
> https://wiki.openjdk.java.net/display/SKARA/FAQ#FAQ-HowdoImodifythechangesinapullrequest?

Thanks for the tip. New patch is pushed as a new commit.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/25


From duke at openjdk.java.net  Wed Dec  8 12:53:14 2021
From: duke at openjdk.java.net (kuaiwei)
Date: Wed, 8 Dec 2021 12:53:14 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr
 around calls [v3]
In-Reply-To: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
Message-ID: <Q51lZRNgxBwCy1SXd3PNLoqtGXv6fWOkhOXuSh-A7eA=.45a129e9-2c40-4707-b65d-48353998712d@github.com>

> It seems zr(x0) is used as stack alignment when saving/restoring registers around calls. But it's unnecessary to ld/st x0 from/to stack. We just need reserve a stack slot in case alignment is required.

kuaiwei has updated the pull request incrementally with one additional commit since the last revision:

fix code style

-------------

Changes:
- all: https://git.openjdk.java.net/riscv-port/pull/25/files
- new: https://git.openjdk.java.net/riscv-port/pull/25/files/ddc32f4e..c64168c4

Webrevs:
- full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=25&range=02
- incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=25&range=01-02

Stats: 3 lines in 1 file changed: 0 ins; 2 del; 1 mod
Patch: https://git.openjdk.java.net/riscv-port/pull/25.diff
Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/25/head:pull/25

PR: https://git.openjdk.java.net/riscv-port/pull/25


From fyang at openjdk.java.net  Wed Dec  8 14:17:50 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Wed, 8 Dec 2021 14:17:50 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr
 around calls [v2]
In-Reply-To: <IXw6CiHLNItRV1tQrJDDk_u5ImvlP8nU8s-gqS-zrPk=.fc66503c-58a0-406f-ba68-9b2b6984c6e4@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
 <EsXYUgWFqFEVM2EtQrpfR6F6CHfzVkoPJFRaPKFkbes=.c995ae05-3dfd-43ed-805c-b98c0ccec8e4@github.com>
 <IXw6CiHLNItRV1tQrJDDk_u5ImvlP8nU8s-gqS-zrPk=.fc66503c-58a0-406f-ba68-9b2b6984c6e4@github.com>
Message-ID: <ivAun_uS_csGB_R1ElUyawG5mNxMNVWtfEOftDS8q9w=.e62ac5e3-b281-4aac-8ffc-0d1385803490@github.com>

On Wed, 8 Dec 2021 12:49:39 GMT, kuaiwei <duke at openjdk.java.net> wrote:

> >
>
> Hi Felix, the patch passed tier1 test in qemu with fastdebug build.

Thank you. Could you please add this to the PR description?

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/25


From duke at openjdk.java.net  Thu Dec  9 09:20:16 2021
From: duke at openjdk.java.net (kuaiwei)
Date: Thu, 9 Dec 2021 09:20:16 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr
 around calls [v3]
In-Reply-To: <9LTW2jLmkyWRk5F3zuezkISTdUxitnGgG-Kdf85OfoY=.5959c13f-ef3d-4219-8bfc-5941317d16db@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
 <Q51lZRNgxBwCy1SXd3PNLoqtGXv6fWOkhOXuSh-A7eA=.45a129e9-2c40-4707-b65d-48353998712d@github.com>
 <9LTW2jLmkyWRk5F3zuezkISTdUxitnGgG-Kdf85OfoY=.5959c13f-ef3d-4219-8bfc-5941317d16db@github.com>
Message-ID: <VUgbFbe7t3acJupiXpLOiqLCR3Uc_rmaLNpKA7ovLZ8=.ed151951-bdc9-4772-901d-8555ca59f515@github.com>

On Thu, 9 Dec 2021 08:22:27 GMT, Fei Yang <fyang at openjdk.org> wrote:

> Looks good.

Thanks.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/25


From fyang at openjdk.java.net  Thu Dec  9 08:25:17 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Thu, 9 Dec 2021 08:25:17 GMT
Subject: [riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr
 around calls [v3]
In-Reply-To: <Q51lZRNgxBwCy1SXd3PNLoqtGXv6fWOkhOXuSh-A7eA=.45a129e9-2c40-4707-b65d-48353998712d@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
 <Q51lZRNgxBwCy1SXd3PNLoqtGXv6fWOkhOXuSh-A7eA=.45a129e9-2c40-4707-b65d-48353998712d@github.com>
Message-ID: <9LTW2jLmkyWRk5F3zuezkISTdUxitnGgG-Kdf85OfoY=.5959c13f-ef3d-4219-8bfc-5941317d16db@github.com>

On Wed, 8 Dec 2021 12:53:14 GMT, kuaiwei <duke at openjdk.java.net> wrote:

>> It seems zr(x0) is used as stack alignment when saving/restoring registers around calls. But it's unnecessary to ld/st x0 from/to stack. We just need reserve a stack slot in case alignment is required.
>
> kuaiwei has updated the pull request incrementally with one additional commit since the last revision:
>
>   fix code style

Looks good.

-------------

Marked as reviewed by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/25


From fyang at openjdk.java.net  Thu Dec  9 02:40:16 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Thu, 9 Dec 2021 02:40:16 GMT
Subject: [riscv-port] RFR: 8278387: riscv: Implement UseHeavyMonitors
 consistently
In-Reply-To: <z6dEJuglIVNiHCV27ozrua3P_v-GvcIw_FFoEtr5gho=.e5a7409e-6bd3-4add-9810-00b928255218@github.com>
References: <z6dEJuglIVNiHCV27ozrua3P_v-GvcIw_FFoEtr5gho=.e5a7409e-6bd3-4add-9810-00b928255218@github.com>
Message-ID: <qE2NhvEbl5ypbVuKX4NkmYxSpWfrWVZvDlpImdkRSxs=.16f9a3ae-ef3c-450d-9c7c-b6aac341b903@github.com>

On Wed, 8 Dec 2021 09:42:40 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> Make hotspot always use inflated monitors consistently if the flag UseHeavyMonitors is true. The riscv platform should follow https://bugs.openjdk.java.net/browse/JDK-8276901.
>
> Hotspot and jdk tier1 passed on the unmatched board. All jtreg tests were tested without new failures.

Looks good.

-------------

Marked as reviewed by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/26


From yadongwang at openjdk.java.net  Wed Dec  8 09:50:01 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Wed, 8 Dec 2021 09:50:01 GMT
Subject: [riscv-port] RFR: 8278387: riscv: Implement UseHeavyMonitors
 consistently
Message-ID: <z6dEJuglIVNiHCV27ozrua3P_v-GvcIw_FFoEtr5gho=.e5a7409e-6bd3-4add-9810-00b928255218@github.com>

Make hotspot always use inflated monitors consistently if the flag UseHeavyMonitors is true. The riscv platform should follow https://bugs.openjdk.java.net/browse/JDK-8276901.

-------------

Commit messages:
- 8278387: riscv: Implement UseHeavyMonitors consistently

Changes: https://git.openjdk.java.net/riscv-port/pull/26/files
Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=26&range=00
Issue: https://bugs.openjdk.java.net/browse/JDK-8278387
Stats: 129 lines in 6 files changed: 40 ins; 20 del; 69 mod
Patch: https://git.openjdk.java.net/riscv-port/pull/26.diff
Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/26/head:pull/26

PR: https://git.openjdk.java.net/riscv-port/pull/26


From duke at openjdk.java.net  Thu Dec  9 09:30:20 2021
From: duke at openjdk.java.net (kuaiwei)
Date: Thu, 9 Dec 2021 09:30:20 GMT
Subject: [riscv-port] Integrated: 8278337: riscv: remove unnecessary ld/sd zr
 around calls
In-Reply-To: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
References: <E4j1EShOWQ0Sgx0manSiDqzLOz1yhITW2Rz_ybWL8Pc=.e8b2f431-f5de-4af2-987b-12ef3e2f38a6@github.com>
Message-ID: <3ELvFOnQ_zHeoeMw1WLyHYssnUDYXlJNKKVloIEhMHk=.313d88fd-7e77-4b7a-b95a-ce357127455a@github.com>

On Tue, 7 Dec 2021 11:21:00 GMT, kuaiwei <duke at openjdk.java.net> wrote:

> It seems zr(x0) is used as stack alignment when saving/restoring registers around calls. But it's unnecessary to ld/st x0 from/to stack. We just need reserve a stack slot in case alignment is required. It passed tier1 tests with fastdebug in qemu.

This pull request has now been integrated.

Changeset: 1a437757
Author:    kuaiwei.kw <kuaiwei.kw at alibaba-inc.com>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/1a437757945ae61524d47e300e0395c02270e18a
Stats:     20 lines in 2 files changed: 4 ins; 10 del; 6 mod

8278337: riscv: remove unnecessary ld/sd zr around calls

Reviewed-by: fyang

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/25

From yadongwang at openjdk.java.net  Thu Dec  9 02:59:31 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Thu, 9 Dec 2021 02:59:31 GMT
Subject: [riscv-port] Integrated: 8278387: riscv: Implement UseHeavyMonitors
 consistently
In-Reply-To: <z6dEJuglIVNiHCV27ozrua3P_v-GvcIw_FFoEtr5gho=.e5a7409e-6bd3-4add-9810-00b928255218@github.com>
References: <z6dEJuglIVNiHCV27ozrua3P_v-GvcIw_FFoEtr5gho=.e5a7409e-6bd3-4add-9810-00b928255218@github.com>
Message-ID: <JmID1Ay-uepcYrVFk2JBstMBoKisfw_-iKxc2pPZjUs=.0e11d662-c31e-417a-85e9-a6c9a2c40fa0@github.com>

On Wed, 8 Dec 2021 09:42:40 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> Make hotspot always use inflated monitors consistently if the flag UseHeavyMonitors is true. The riscv platform should follow https://bugs.openjdk.java.net/browse/JDK-8276901.
>
> Hotspot and jdk tier1 passed on the unmatched board. All jtreg tests were tested without new failures.

This pull request has now been integrated.

Changeset: 62c9bc7c
Author:    Yadong Wang <yadongwang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/62c9bc7cd05e776afe447ed3a09cf08af9d5a7d1
Stats:     129 lines in 6 files changed: 40 ins; 20 del; 69 mod

8278387: riscv: Implement UseHeavyMonitors consistently

Reviewed-by: fyang

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/26

From fjiang at openjdk.java.net  Thu Dec  9 10:59:24 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Thu, 9 Dec 2021 10:59:24 GMT
Subject: [riscv-port] Integrated: 8278474: riscv: Enable two more jtreg hotspot
 tests
In-Reply-To: <UR-g8LjahnxhZ3EccYweQeeyWRrrkN-qFdZ3x2B6EpQ=.e9985ab6-1c3d-4574-afc7-3b05a219b111@github.com>
References: <UR-g8LjahnxhZ3EccYweQeeyWRrrkN-qFdZ3x2B6EpQ=.e9985ab6-1c3d-4574-afc7-3b05a219b111@github.com>
Message-ID: <Q9ZlMQVIEr6y6onBzv9n7rYDjjLrS0654HglaO4U3ss=.40645055-2097-4537-974a-0715c9c7f6f4@github.com>

On Thu, 9 Dec 2021 09:17:29 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> Some jtreg tests are arch dependent, enable two more hotspot tests on riscv:
> - test/hotspot/jtreg/compiler/c2/TestBit.java
> - test/hotspot/jtreg/serviceability/AsyncGetCallTrace/MyPackage/ASGCTBaseTest.java
>
> The above tests are passed on unmatched board and QEMU user mode.

This pull request has now been integrated.

Changeset: 9d030632
Author:    Feilong Jiang <fjiang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/9d030632a1359b20ac71cad7b228b76bbff29f1d
Stats:     4 lines in 2 files changed: 1 ins; 0 del; 3 mod

8278474: riscv: Enable two more jtreg hotspot tests

Reviewed-by: fyang

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/27

From fjiang at openjdk.java.net  Thu Dec  9 09:23:50 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Thu, 9 Dec 2021 09:23:50 GMT
Subject: [riscv-port] RFR: 8278474: riscv: Enable two more jtreg hotspot tests
Message-ID: <UR-g8LjahnxhZ3EccYweQeeyWRrrkN-qFdZ3x2B6EpQ=.e9985ab6-1c3d-4574-afc7-3b05a219b111@github.com>

Some jtreg tests are arch dependent, enable two more hotspot tests on riscv:
- test/hotspot/jtreg/compiler/c2/TestBit.java
- test/hotspot/jtreg/serviceability/AsyncGetCallTrace/MyPackage/ASGCTBaseTest.java

The above tests are passed on unmatched board and QEMU user mode.

-------------

Commit messages:
- 8278474: riscv: Enable two more jtreg hotspot tests

Changes: https://git.openjdk.java.net/riscv-port/pull/27/files
Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=27&range=00
Issue: https://bugs.openjdk.java.net/browse/JDK-8278474
Stats: 4 lines in 2 files changed: 1 ins; 0 del; 3 mod
Patch: https://git.openjdk.java.net/riscv-port/pull/27.diff
Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/27/head:pull/27

PR: https://git.openjdk.java.net/riscv-port/pull/27


From fyang at openjdk.java.net  Thu Dec  9 10:47:33 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Thu, 9 Dec 2021 10:47:33 GMT
Subject: [riscv-port] RFR: 8278474: riscv: Enable two more jtreg hotspot
 tests
In-Reply-To: <UR-g8LjahnxhZ3EccYweQeeyWRrrkN-qFdZ3x2B6EpQ=.e9985ab6-1c3d-4574-afc7-3b05a219b111@github.com>
References: <UR-g8LjahnxhZ3EccYweQeeyWRrrkN-qFdZ3x2B6EpQ=.e9985ab6-1c3d-4574-afc7-3b05a219b111@github.com>
Message-ID: <Xuy_-3BXMr25IOWN7D1juaERXzmLVr9GgwxQ7kOcpK4=.b7c23512-2cf2-4c6a-8633-fabea2a4f4d2@github.com>

On Thu, 9 Dec 2021 09:17:29 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> Some jtreg tests are arch dependent, enable two more hotspot tests on riscv:
> - test/hotspot/jtreg/compiler/c2/TestBit.java
> - test/hotspot/jtreg/serviceability/AsyncGetCallTrace/MyPackage/ASGCTBaseTest.java
>
> The above tests are passed on unmatched board and QEMU user mode.

Looks good.

-------------

Marked as reviewed by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/27


From xlinzheng at openjdk.java.net  Tue Dec 14 04:32:56 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Tue, 14 Dec 2021 04:32:56 GMT
Subject: [riscv-port] RFR: 8278743: riscv: Remove the x4 register saving logic
 in Java frames
Message-ID: <YvJSZkoiUdPuj0voASL8E-hgWqGneIAG2trhvzAJAbM=.34472275-d074-4ee6-879d-d15b4089e178@github.com>

Hi team,

x4 is the thread pointer register and would be modified by the kernel. With this respect, we shall not modify or change its value. In the riscv-port repo, we have no other modifications for the x4 register so I would recommend removing the x4 saving logic in java frames. I have verified this change along with other patches under jdk/hotspot full tiers on different boards and qemu.

BTW, due to the logic that can automatically adjust the sp to 16-byte aligned[1], it is safe to change the `sp_after_call_off` to an odd number.

[1] https://github.com/openjdk/riscv-port/blob/riscv-port/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp#L277

Thanks,
Xiaolin

-------------

Commit messages:
 - Remove x4 in java frames

Changes: https://git.openjdk.java.net/riscv-port/pull/29/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=29&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278743
  Stats: 32 lines in 2 files changed: 0 ins; 6 del; 26 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/29.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/29/head:pull/29

PR: https://git.openjdk.java.net/riscv-port/pull/29

From yadongwang at openjdk.java.net  Tue Dec 14 06:36:41 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Tue, 14 Dec 2021 06:36:41 GMT
Subject: [riscv-port] RFR: 8278743: riscv: Remove the x4 register saving
 logic in Java frames
In-Reply-To: <YvJSZkoiUdPuj0voASL8E-hgWqGneIAG2trhvzAJAbM=.34472275-d074-4ee6-879d-d15b4089e178@github.com>
References: <YvJSZkoiUdPuj0voASL8E-hgWqGneIAG2trhvzAJAbM=.34472275-d074-4ee6-879d-d15b4089e178@github.com>
Message-ID: <PMkK9kjr4aROrHWxHGPC9U68YBng3-RDnzZe_zF95rk=.191b3e3e-12c1-4505-85a7-3e7244c63412@github.com>

On Tue, 14 Dec 2021 04:27:20 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
> 
> x4 is the thread pointer register and would be modified by the kernel. With this respect, we shall not modify or change its value. In the riscv-port repo, we have no other modifications for the x4 register so I would recommend removing the x4 saving logic in java frames. I have verified this change along with other patches under jdk/hotspot full tiers on different boards and qemu.
> 
> BTW, due to the logic that can automatically adjust the sp to 16-byte aligned[1], it is safe to change the `sp_after_call_off` to an odd number.
> 
> [1] https://github.com/openjdk/riscv-port/blob/riscv-port/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp#L277
> 
> Thanks,
> Xiaolin

lgtm

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/29

From fyang at openjdk.java.net  Tue Dec 14 08:31:42 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Tue, 14 Dec 2021 08:31:42 GMT
Subject: [riscv-port] RFR: 8278743: riscv: Remove the x4 register saving
 logic in Java frames
In-Reply-To: <YvJSZkoiUdPuj0voASL8E-hgWqGneIAG2trhvzAJAbM=.34472275-d074-4ee6-879d-d15b4089e178@github.com>
References: <YvJSZkoiUdPuj0voASL8E-hgWqGneIAG2trhvzAJAbM=.34472275-d074-4ee6-879d-d15b4089e178@github.com>
Message-ID: <CXx2XmMtsw2pC90NYCOa9IQFlKlXz8-PL1MT3IuXM8U=.7c060f58-a7ee-461f-9a60-1a3e82a53374@github.com>

On Tue, 14 Dec 2021 04:27:20 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
> 
> x4 is the thread pointer register and would be modified by the kernel. With this respect, we shall not modify or change its value. In the riscv-port repo, we have no other modifications for the x4 register so I would recommend removing the x4 saving logic in java frames. I have verified this change along with other patches under jdk/hotspot full tiers on different boards and qemu.
> 
> BTW, due to the logic that can automatically adjust the sp to 16-byte aligned[1], it is safe to change the `sp_after_call_off` to an odd number.
> 
> [1] https://github.com/openjdk/riscv-port/blob/riscv-port/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp#L277
> 
> Thanks,
> Xiaolin

Looks good. Thanks.

-------------

Marked as reviewed by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/29

From xlinzheng at openjdk.java.net  Tue Dec 14 08:34:41 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Tue, 14 Dec 2021 08:34:41 GMT
Subject: [riscv-port] RFR: 8278743: riscv: Remove the x4 register saving
 logic in Java frames
In-Reply-To: <YvJSZkoiUdPuj0voASL8E-hgWqGneIAG2trhvzAJAbM=.34472275-d074-4ee6-879d-d15b4089e178@github.com>
References: <YvJSZkoiUdPuj0voASL8E-hgWqGneIAG2trhvzAJAbM=.34472275-d074-4ee6-879d-d15b4089e178@github.com>
Message-ID: <bgfhdddEpt5LimZFGQtlLebUfm6sMUVYR_OY2_Hj9qk=.acdb0b60-3c8e-4082-aaba-d23272fc7317@github.com>

On Tue, 14 Dec 2021 04:27:20 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
> 
> x4 is the thread pointer register and would be modified by the kernel. With this respect, we shall not modify or change its value. In the riscv-port repo, we have no other modifications for the x4 register so I would recommend removing the x4 saving logic in java frames. I have verified this change along with other patches under jdk/hotspot full tiers on different boards and qemu.
> 
> BTW, due to the logic that can automatically adjust the sp to 16-byte aligned[1], it is safe to change the `sp_after_call_off` to an odd number.
> 
> [1] https://github.com/openjdk/riscv-port/blob/riscv-port/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp#L277
> 
> Thanks,
> Xiaolin

Quite thanks for the reviews.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/29

From xlinzheng at openjdk.java.net  Tue Dec 14 08:51:45 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Tue, 14 Dec 2021 08:51:45 GMT
Subject: [riscv-port] Integrated: 8278743: riscv: Remove the x4 register saving
 logic in Java frames
In-Reply-To: <YvJSZkoiUdPuj0voASL8E-hgWqGneIAG2trhvzAJAbM=.34472275-d074-4ee6-879d-d15b4089e178@github.com>
References: <YvJSZkoiUdPuj0voASL8E-hgWqGneIAG2trhvzAJAbM=.34472275-d074-4ee6-879d-d15b4089e178@github.com>
Message-ID: <JJh35VX5CQw7rEQ22LVFvmAaL7vb09r3jBJ6nPJrR34=.f85f418d-5578-40a9-81b8-e1a4efa7d419@github.com>

On Tue, 14 Dec 2021 04:27:20 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
> 
> x4 is the thread pointer register and would be modified by the kernel. With this respect, we shall not modify or change its value. In the riscv-port repo, we have no other modifications for the x4 register so I would recommend removing the x4 saving logic in java frames. I have verified this change along with other patches under jdk/hotspot full tiers on different boards and qemu.
> 
> BTW, due to the logic that can automatically adjust the sp to 16-byte aligned[1], it is safe to change the `sp_after_call_off` to an odd number.
> 
> [1] https://github.com/openjdk/riscv-port/blob/riscv-port/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp#L277
> 
> Thanks,
> Xiaolin

This pull request has now been integrated.

Changeset: 3a9a1eb9
Author:    Xiaolin Zheng <xlinzheng at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/3a9a1eb94bf737c4355d473b2a86b03c46fbaa99
Stats:     32 lines in 2 files changed: 0 ins; 6 del; 26 mod

8278743: riscv: Remove the x4 register saving logic in Java frames

Reviewed-by: fyang

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/29

From yadongwang at openjdk.java.net  Tue Dec 14 09:22:50 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Tue, 14 Dec 2021 09:22:50 GMT
Subject: [riscv-port] RFR: 8278041: riscv: Use t2 as the dedicated machine
 flags register in C2 [v2]
In-Reply-To: <6nmr2Yh797p1XjsyRDfGIqp6WfDbJk-o1dR6mTuxbQk=.d1f741ba-bda9-4228-8cb0-43d0e23b0f32@github.com>
References: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>
 <6nmr2Yh797p1XjsyRDfGIqp6WfDbJk-o1dR6mTuxbQk=.d1f741ba-bda9-4228-8cb0-43d0e23b0f32@github.com>
Message-ID: <536CGHR67NgZMWawL42SgZx3p8xo4GynNJf6XGvUmfk=.d21cee37-af34-47ff-b596-761a2b06b037@github.com>

On Wed, 1 Dec 2021 09:35:26 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

>> There are non-allocatable registers t0 and t1 in C2, frequently used as temporary registers for common code snipptes. Meanwhile, C2 use t1 as the flags register, so that many instructs using t1 as a temporary register must declare the data flow effect of t1 which is not part of a match rule. So we can reserve t2 and use it as the machine flags register in C2 instead, to reduce the probability of misuse of t1 without declaring the data flow effect.
>
> Yadong Wang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   8278041: riscv: Use t2 as the dedicated machine flags register in C2(2)

I'll close this pr first, and reopen later if needed.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/21

From yadongwang at openjdk.java.net  Tue Dec 14 09:22:51 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Tue, 14 Dec 2021 09:22:51 GMT
Subject: [riscv-port] Withdrawn: 8278041: riscv: Use t2 as the dedicated
 machine flags register in C2
In-Reply-To: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>
References: <aXgP1X5yZxWqqwkJgbK-4xsi1GL0XLBqxgGbFli5JxQ=.a8d21966-5e4f-42c5-87e1-c2718137e407@github.com>
Message-ID: <uRNM1cWenGqOCHY7Ufe-cE57Mwpm2jq-z5UC0pRbG0c=.5c31bed4-8931-4111-8269-402ccb8930dc@github.com>

On Wed, 1 Dec 2021 07:56:54 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> There are non-allocatable registers t0 and t1 in C2, frequently used as temporary registers for common code snipptes. Meanwhile, C2 use t1 as the flags register, so that many instructs using t1 as a temporary register must declare the data flow effect of t1 which is not part of a match rule. So we can reserve t2 and use it as the machine flags register in C2 instead, to reduce the probability of misuse of t1 without declaring the data flow effect.

This pull request has been closed without being integrated.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/21

From fjiang at openjdk.java.net  Wed Dec 15 02:41:49 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Wed, 15 Dec 2021 02:41:49 GMT
Subject: [riscv-port] RFR: 8278832: riscv: Inconsistency of Java frame offset
 definition in jdk.hotspot.agent
Message-ID: <TZ0l99G_j07bgPwemeORxeDL7Q3F7aO7CMYUkpGaiko=.9179b213-5d60-4123-87dc-ec090ac1fd20@github.com>

The Java frame definition was refactored in https://github.com/openjdk/jdk-sandbox/commit/db2415748747a0912749bb8fc160a8948021a924 to make Java frame offset the same as C frame. In jdk.hotspot.agent, there is another Java frame definition based on the old Java frame offset, which causes jstack stack walking error. These definitions should also be updated.

Two tests passed after this fixing:
- test/hotspot/jtreg/serviceability/sa/ClhsdbCDSCore.java
- test/hotspot/jtreg/serviceability/sa/ClhsdbFindPC.java

-------------

Commit messages:
 - 8278832: riscv: Inconsistency of Java frame offset definition in jdk.hotspot.agent

Changes: https://git.openjdk.java.net/riscv-port/pull/30/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=30&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278832
  Stats: 5 lines in 1 file changed: 0 ins; 0 del; 5 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/30.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/30/head:pull/30

PR: https://git.openjdk.java.net/riscv-port/pull/30

From xlinzheng at openjdk.java.net  Wed Dec 15 03:05:44 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Wed, 15 Dec 2021 03:05:44 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving
 logic in register savers
Message-ID: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>

Hi team,

x3 is the global pointer register used to reference global variables in C++ code, generated by linker; and x4 is the thread pointer register and would be modified by the kernel. In the riscv-port repo, we have no other modifications for the x3 & x4 registers so I would recommend removing the x3 & x4 saving logic in register savers. Previously verified along with other patches under full tiers jdk/hotspot on boards, and verified a simple `test/jtreg/hotspot/compiler` after fixing conflicts with [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25).

BTW since we remove both two registers together, sp remains 16-byte aligned without other changes in stack frames.

Thanks,
Xiaolin

-------------

Commit messages:
 - Remove the x3 x4 in register savers

Changes: https://git.openjdk.java.net/riscv-port/pull/31/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=31&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278833
  Stats: 26 lines in 3 files changed: 1 ins; 0 del; 25 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/31.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/31/head:pull/31

PR: https://git.openjdk.java.net/riscv-port/pull/31

From yadongwang at openjdk.java.net  Wed Dec 15 03:09:24 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Wed, 15 Dec 2021 03:09:24 GMT
Subject: [riscv-port] RFR: 8278832: riscv: Inconsistency of Java frame
 offset definition in jdk.hotspot.agent
In-Reply-To: <TZ0l99G_j07bgPwemeORxeDL7Q3F7aO7CMYUkpGaiko=.9179b213-5d60-4123-87dc-ec090ac1fd20@github.com>
References: <TZ0l99G_j07bgPwemeORxeDL7Q3F7aO7CMYUkpGaiko=.9179b213-5d60-4123-87dc-ec090ac1fd20@github.com>
Message-ID: <PWFpMgCjRlSSIhrx1s6OywToOXES0wN4GRuWOFl8kzk=.2cd9d987-86c8-479d-9a8c-0311ef89b78a@github.com>

On Wed, 15 Dec 2021 02:35:05 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> The Java frame definition was refactored in https://github.com/openjdk/jdk-sandbox/commit/db2415748747a0912749bb8fc160a8948021a924 to make Java frame offset the same as C frame. In jdk.hotspot.agent, there is another Java frame definition based on the old Java frame offset, which causes jstack stack walking error. These definitions should also be updated.
> 
> Two tests passed after this fixing:
> - test/hotspot/jtreg/serviceability/sa/ClhsdbCDSCore.java
> - test/hotspot/jtreg/serviceability/sa/ClhsdbFindPC.java

lgtm

-------------

Marked as reviewed by yadongwang (Author).

PR: https://git.openjdk.java.net/riscv-port/pull/30

From yzhu at openjdk.java.net  Wed Dec 15 03:18:31 2021
From: yzhu at openjdk.java.net (Yanhong Zhu)
Date: Wed, 15 Dec 2021 03:18:31 GMT
Subject: [riscv-port] RFR: 8278832: riscv: Inconsistency of Java frame
 offset definition in jdk.hotspot.agent
In-Reply-To: <TZ0l99G_j07bgPwemeORxeDL7Q3F7aO7CMYUkpGaiko=.9179b213-5d60-4123-87dc-ec090ac1fd20@github.com>
References: <TZ0l99G_j07bgPwemeORxeDL7Q3F7aO7CMYUkpGaiko=.9179b213-5d60-4123-87dc-ec090ac1fd20@github.com>
Message-ID: <T8yrLB3G3kAzq-791r9PLST-oKFipyakU4h3iEyJ3z8=.7822bad7-b870-4e5b-a096-646e0bcdd126@github.com>

On Wed, 15 Dec 2021 02:35:05 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> The Java frame definition was refactored in https://github.com/openjdk/jdk-sandbox/commit/db2415748747a0912749bb8fc160a8948021a924 to make Java frame offset the same as C frame. In jdk.hotspot.agent, there is another Java frame definition based on the old Java frame offset, which causes jstack stack walking error. These definitions should also be updated.
> 
> Two tests passed after this fixing:
> - test/hotspot/jtreg/serviceability/sa/ClhsdbCDSCore.java
> - test/hotspot/jtreg/serviceability/sa/ClhsdbFindPC.java

Looks good.

-------------

Marked as reviewed by yzhu (Author).

PR: https://git.openjdk.java.net/riscv-port/pull/30

From yadongwang at openjdk.java.net  Wed Dec 15 07:53:30 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Wed, 15 Dec 2021 07:53:30 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers
In-Reply-To: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
Message-ID: <R5ReyJSwGHQbTBT637Cz73YC6dI_gDyTfGRIuiZwjTI=.e4eeed31-beeb-4538-a263-e4ef223731d8@github.com>

On Wed, 15 Dec 2021 02:59:37 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
> 
> x3 is the global pointer register used to reference global variables in C++ code, generated by linker; and x4 is the thread pointer register and would be modified by the kernel. In the riscv-port repo, we have no other modifications for the x3 & x4 registers so I would recommend removing the x3 & x4 saving logic in register savers. Previously verified along with other patches under full tiers jdk/hotspot on boards, and verified a simple `test/jtreg/hotspot/compiler` after fixing conflicts with [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25).
> 
> BTW since we remove both two registers together, sp remains 16-byte aligned without other changes in stack frames.
> 
> Thanks,
> Xiaolin

src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp line 289:

> 287:   __ block_comment("save_live_registers");
> 288: 
> 289:   // if the number of pushed regs is odd, zr will be added

`// if the number of pushed regs is odd, zr will be added` is out-of-date after JDK-8278337.

src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp line 352:

> 350:   }
> 351: 
> 352:   // we save x0, x5 ~ x31, except x1, x2, x3, x4

Are we still saving x0 now?

src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp line 198:

> 196:   for (int i = 5; i < RegisterImpl::number_of_registers; i++, sp_offset_in_slots += step_in_slots) {
> 197:     Register r = as_Register(i);
> 198:     if (r != xthread && r != t0 && r != t1) {

Why not start the loop from x7?

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/31

From xlinzheng at openjdk.java.net  Wed Dec 15 09:02:03 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Wed, 15 Dec 2021 09:02:03 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers [v2]
In-Reply-To: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
Message-ID: <-vouM1s0vp_lvBfu85ssS9NLQnraflUwJe8l13-yj-M=.ab053efc-e656-46e4-9d7b-1fec6f7382ad@github.com>

> Hi team,
> 
> x3 is the global pointer register used to reference global variables in C++ code, generated by linker; and x4 is the thread pointer register and would be modified by the kernel. In the riscv-port repo, we have no other modifications for the x3 & x4 registers so I would recommend removing the x3 & x4 saving logic in register savers. Previously verified along with other patches under full tiers jdk/hotspot on boards, and verified a simple `test/jtreg/hotspot/compiler` after fixing conflicts with [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25).
> 
> BTW since we remove both two registers together, sp remains 16-byte aligned without other changes in stack frames.
> 
> Thanks,
> Xiaolin

Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:

  Fix comments for JDK-8278337 and commit other improvements as proposed

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/31/files
  - new: https://git.openjdk.java.net/riscv-port/pull/31/files/4602a4d9..bdb5fba3

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=31&range=01
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=31&range=00-01

  Stats: 18 lines in 2 files changed: 4 ins; 3 del; 11 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/31.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/31/head:pull/31

PR: https://git.openjdk.java.net/riscv-port/pull/31

From xlinzheng at openjdk.java.net  Wed Dec 15 09:02:06 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Wed, 15 Dec 2021 09:02:06 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers [v2]
In-Reply-To: <R5ReyJSwGHQbTBT637Cz73YC6dI_gDyTfGRIuiZwjTI=.e4eeed31-beeb-4538-a263-e4ef223731d8@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
 <R5ReyJSwGHQbTBT637Cz73YC6dI_gDyTfGRIuiZwjTI=.e4eeed31-beeb-4538-a263-e4ef223731d8@github.com>
Message-ID: <Bq56UMpLBwzOipuGwo51ZE8od0dTQsnTv3Ua32lb_uU=.862a6cc5-1bbf-4966-b946-003e8fc87320@github.com>

On Wed, 15 Dec 2021 03:11:21 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

>> Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Fix comments for JDK-8278337 and commit other improvements as proposed
>
> src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp line 289:
> 
>> 287:   __ block_comment("save_live_registers");
>> 288: 
>> 289:   // if the number of pushed regs is odd, zr will be added
> 
> `// if the number of pushed regs is odd, zr will be added` is out-of-date after JDK-8278337.

Right -- changed.

> src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp line 352:
> 
>> 350:   }
>> 351: 
>> 352:   // we save x0, x5 ~ x31, except x1, x2, x3, x4
> 
> Are we still saving x0 now?

Right -- changed.

> src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp line 198:
> 
>> 196:   for (int i = 5; i < RegisterImpl::number_of_registers; i++, sp_offset_in_slots += step_in_slots) {
>> 197:     Register r = as_Register(i);
>> 198:     if (r != xthread && r != t0 && r != t1) {
> 
> Why not start the loop from x7?

Thanks for the nice reminder -- changed.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/31

From fyang at openjdk.java.net  Wed Dec 15 09:02:30 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Wed, 15 Dec 2021 09:02:30 GMT
Subject: [riscv-port] RFR: 8278832: riscv: Inconsistency of Java frame
 offset definition in jdk.hotspot.agent
In-Reply-To: <TZ0l99G_j07bgPwemeORxeDL7Q3F7aO7CMYUkpGaiko=.9179b213-5d60-4123-87dc-ec090ac1fd20@github.com>
References: <TZ0l99G_j07bgPwemeORxeDL7Q3F7aO7CMYUkpGaiko=.9179b213-5d60-4123-87dc-ec090ac1fd20@github.com>
Message-ID: <9A2ru9JgOx47qmWio4aDWjpTDYeNuBnER_ZVDBAY64Y=.e37c278d-a976-4ee5-a5c0-d520929778af@github.com>

On Wed, 15 Dec 2021 02:35:05 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> The Java frame definition was refactored in https://github.com/openjdk/jdk-sandbox/commit/db2415748747a0912749bb8fc160a8948021a924 to make Java frame offset the same as C frame. In jdk.hotspot.agent, there is another Java frame definition based on the old Java frame offset, which causes jstack stack walking error. These definitions should also be updated.
> 
> Two tests passed after this fixing:
> - test/hotspot/jtreg/serviceability/sa/ClhsdbCDSCore.java
> - test/hotspot/jtreg/serviceability/sa/ClhsdbFindPC.java

Marked as reviewed by fyang (Lead).

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/30

From xlinzheng at openjdk.java.net  Wed Dec 15 09:05:18 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Wed, 15 Dec 2021 09:05:18 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers [v2]
In-Reply-To: <Bq56UMpLBwzOipuGwo51ZE8od0dTQsnTv3Ua32lb_uU=.862a6cc5-1bbf-4966-b946-003e8fc87320@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
 <R5ReyJSwGHQbTBT637Cz73YC6dI_gDyTfGRIuiZwjTI=.e4eeed31-beeb-4538-a263-e4ef223731d8@github.com>
 <Bq56UMpLBwzOipuGwo51ZE8od0dTQsnTv3Ua32lb_uU=.862a6cc5-1bbf-4966-b946-003e8fc87320@github.com>
Message-ID: <BeROT4pbTS7ytTJGOqzNI_J4WZGCN5kJulQKjYdrdH8=.90ea9f2d-f844-41ba-b4e6-f42ff805b86f@github.com>

On Wed, 15 Dec 2021 08:57:45 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp line 198:
>> 
>>> 196:   for (int i = 5; i < RegisterImpl::number_of_registers; i++, sp_offset_in_slots += step_in_slots) {
>>> 197:     Register r = as_Register(i);
>>> 198:     if (r != xthread && r != t0 && r != t1) {
>> 
>> Why not start the loop from x7?
>
> Thanks for the nice reminder -- changed.

Need some testing work for the new change -- I will ping this thread after tests are done.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/31

From yzhu at openjdk.java.net  Wed Dec 15 09:06:51 2021
From: yzhu at openjdk.java.net (Yanhong Zhu)
Date: Wed, 15 Dec 2021 09:06:51 GMT
Subject: [riscv-port] RFR: 8278547: riscv: Refactor moving assembler functions
 for vector instructions into separate file
Message-ID: <IV91utXqA6lhy--_IyrjK7qSWDjXdatNZeZWROGJ8iE=.68dec187-e575-4396-b104-7d5f9192a376@github.com>

RISCV have several feature extensions: RVV, RVC and RVB.
Work in under progress to support those features in Hotspot JVM.
For maintenance purposes, we should move assembler functions for specific feature into separate file.
This patch refactors existing code moving assembler functions for RVV into feature-specific files.

-------------

Commit messages:
 - 8278547: riscv: Refactor moving assembler functions for vector instructions into separate file

Changes: https://git.openjdk.java.net/riscv-port/pull/32/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=32&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278547
  Stats: 1349 lines in 3 files changed: 696 ins; 651 del; 2 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/32.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/32/head:pull/32

PR: https://git.openjdk.java.net/riscv-port/pull/32

From fjiang at openjdk.java.net  Wed Dec 15 09:38:20 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Wed, 15 Dec 2021 09:38:20 GMT
Subject: [riscv-port] Integrated: 8278832: riscv: Inconsistency of Java frame
 offset definition in jdk.hotspot.agent
In-Reply-To: <TZ0l99G_j07bgPwemeORxeDL7Q3F7aO7CMYUkpGaiko=.9179b213-5d60-4123-87dc-ec090ac1fd20@github.com>
References: <TZ0l99G_j07bgPwemeORxeDL7Q3F7aO7CMYUkpGaiko=.9179b213-5d60-4123-87dc-ec090ac1fd20@github.com>
Message-ID: <rEHplLTyQM0ZGSfskRMdS2eTiap7VmUx6bGbFyTR_yE=.1ab3ab63-c664-42b0-ace0-71fd44ca0269@github.com>

On Wed, 15 Dec 2021 02:35:05 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> The Java frame definition was refactored in https://github.com/openjdk/jdk-sandbox/commit/db2415748747a0912749bb8fc160a8948021a924 to make Java frame offset the same as C frame. In jdk.hotspot.agent, there is another Java frame definition based on the old Java frame offset, which causes jstack stack walking error. These definitions should also be updated.
> 
> Two tests passed after this fixing:
> - test/hotspot/jtreg/serviceability/sa/ClhsdbCDSCore.java
> - test/hotspot/jtreg/serviceability/sa/ClhsdbFindPC.java

This pull request has now been integrated.

Changeset: 58dff3e4
Author:    Feilong Jiang <fjiang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/58dff3e46fbb3e9cb57b60e742fd454535254340
Stats:     5 lines in 1 file changed: 0 ins; 0 del; 5 mod

8278832: riscv: Inconsistency of Java frame offset definition in jdk.hotspot.agent

Reviewed-by: yadongwang, yzhu, fyang

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/30

From xlinzheng at openjdk.java.net  Wed Dec 15 11:48:17 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Wed, 15 Dec 2021 11:48:17 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers [v2]
In-Reply-To: <BeROT4pbTS7ytTJGOqzNI_J4WZGCN5kJulQKjYdrdH8=.90ea9f2d-f844-41ba-b4e6-f42ff805b86f@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
 <R5ReyJSwGHQbTBT637Cz73YC6dI_gDyTfGRIuiZwjTI=.e4eeed31-beeb-4538-a263-e4ef223731d8@github.com>
 <Bq56UMpLBwzOipuGwo51ZE8od0dTQsnTv3Ua32lb_uU=.862a6cc5-1bbf-4966-b946-003e8fc87320@github.com>
 <BeROT4pbTS7ytTJGOqzNI_J4WZGCN5kJulQKjYdrdH8=.90ea9f2d-f844-41ba-b4e6-f42ff805b86f@github.com>
Message-ID: <6qAUZuR-KzEeyhpEo5ZR_GHkUDQUlEkbqFXUEaLEbqo=.e4689e5a-b72c-4023-b399-4835b32b72a7@github.com>

On Wed, 15 Dec 2021 09:01:46 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> Thanks for the nice reminder -- changed.
>
> Need some testing work for the new change -- I will ping this thread after tests are done.

`test/jtreg/hotspot/compiler` on Qemu reveals no other errors.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/31

From yadongwang at openjdk.java.net  Thu Dec 16 01:20:25 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Thu, 16 Dec 2021 01:20:25 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers [v2]
In-Reply-To: <-vouM1s0vp_lvBfu85ssS9NLQnraflUwJe8l13-yj-M=.ab053efc-e656-46e4-9d7b-1fec6f7382ad@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
 <-vouM1s0vp_lvBfu85ssS9NLQnraflUwJe8l13-yj-M=.ab053efc-e656-46e4-9d7b-1fec6f7382ad@github.com>
Message-ID: <yHQhAQKkZM2QmX1c5qATUsVTGIG0-Za6aZ_VCyW5y7Y=.b55b2517-0aa9-4efd-9c96-cb0add2583b7@github.com>

On Wed, 15 Dec 2021 09:02:03 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> Hi team,
>> 
>> x3 is the global pointer register used to reference global variables in C++ code, generated by linker; and x4 is the thread pointer register and would be modified by the kernel. In the riscv-port repo, we have no other modifications for the x3 & x4 registers so I would recommend removing the x3 & x4 saving logic in register savers. Previously verified along with other patches under full tiers jdk/hotspot on boards, and verified a simple `test/jtreg/hotspot/compiler` after fixing conflicts with [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25).
>> 
>> BTW since we remove both two registers together, sp remains 16-byte aligned without other changes in stack frames.
>> 
>> Thanks,
>> Xiaolin
>
> Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Fix comments for JDK-8278337 and commit other improvements as proposed

lgtm

-------------

Marked as reviewed by yadongwang (Author).

PR: https://git.openjdk.java.net/riscv-port/pull/31

From yadongwang at openjdk.java.net  Thu Dec 16 01:21:23 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Thu, 16 Dec 2021 01:21:23 GMT
Subject: [riscv-port] RFR: 8278547: riscv: Refactor moving assembler
 functions for vector instructions into separate file
In-Reply-To: <IV91utXqA6lhy--_IyrjK7qSWDjXdatNZeZWROGJ8iE=.68dec187-e575-4396-b104-7d5f9192a376@github.com>
References: <IV91utXqA6lhy--_IyrjK7qSWDjXdatNZeZWROGJ8iE=.68dec187-e575-4396-b104-7d5f9192a376@github.com>
Message-ID: <RN9HP_7Tq14Zprcjpv3rE6LRwWL5MNNVTBd9_LSNR9k=.4c296d9c-daba-4e3d-9773-2eef13776adb@github.com>

On Wed, 15 Dec 2021 08:59:57 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

> RISCV have several feature extensions: RVV, RVC and RVB.
> Work in under progress to support those features in Hotspot JVM.
> For maintenance purposes, we should move assembler functions for specific feature into separate file.
> This patch refactors existing code moving assembler functions for RVV into feature-specific files.
> 
> Hotspot and jdk tier1 passed on the unmatched board. Performed full jtreg tests with qemu without new failures.

lgtm

-------------

Marked as reviewed by yadongwang (Author).

PR: https://git.openjdk.java.net/riscv-port/pull/32

From fjiang at openjdk.java.net  Thu Dec 16 01:26:33 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Thu, 16 Dec 2021 01:26:33 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers [v2]
In-Reply-To: <-vouM1s0vp_lvBfu85ssS9NLQnraflUwJe8l13-yj-M=.ab053efc-e656-46e4-9d7b-1fec6f7382ad@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
 <-vouM1s0vp_lvBfu85ssS9NLQnraflUwJe8l13-yj-M=.ab053efc-e656-46e4-9d7b-1fec6f7382ad@github.com>
Message-ID: <aw8hZHTcYN0d8DfdgsZQQQbvzgk_QtQjxUYHyNHB-J0=.d8f2b421-1f42-4e73-bb72-ebcb7aa734c0@github.com>

On Wed, 15 Dec 2021 09:02:03 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> Hi team,
>> 
>> x3 is the global pointer register used to reference global variables in C++ code, generated by linker; and x4 is the thread pointer register and would be modified by the kernel. In the riscv-port repo, we have no other modifications for the x3 & x4 registers so I would recommend removing the x3 & x4 saving logic in register savers. Previously verified along with other patches under full tiers jdk/hotspot on boards, and verified a simple `test/jtreg/hotspot/compiler` after fixing conflicts with [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25).
>> 
>> BTW since we remove both two registers together, sp remains 16-byte aligned without other changes in stack frames.
>> 
>> Thanks,
>> Xiaolin
>
> Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Fix comments for JDK-8278337 and commit other improvements as proposed

src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp line 337:

> 335:   // if the number of popped regs is odd, the reserved slot for alignment will be removed
> 336:   // integer registers except ra(x1) & sp(x2) & gp(x3) & tp(x4) & x10
> 337:   __ pop_reg(RegSet::range(x5, x9), sp);   // pop zr, x5 ~ x9

Is `zr` will be poped?

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/31

From fyang at openjdk.java.net  Thu Dec 16 01:27:24 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Thu, 16 Dec 2021 01:27:24 GMT
Subject: [riscv-port] RFR: 8278547: riscv: Refactor moving assembler
 functions for vector instructions into separate file
In-Reply-To: <IV91utXqA6lhy--_IyrjK7qSWDjXdatNZeZWROGJ8iE=.68dec187-e575-4396-b104-7d5f9192a376@github.com>
References: <IV91utXqA6lhy--_IyrjK7qSWDjXdatNZeZWROGJ8iE=.68dec187-e575-4396-b104-7d5f9192a376@github.com>
Message-ID: <QavILqY_unvGl3XIBiONeMP7DcaK0AJHw3bDFvbdURM=.763a3b34-0a37-433a-b33c-4e9e3ba8a9d1@github.com>

On Wed, 15 Dec 2021 08:59:57 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

> RISCV have several feature extensions: RVV, RVC and RVB.
> Work in under progress to support those features in Hotspot JVM.
> For maintenance purposes, we should move assembler functions for specific feature into separate file.
> This patch refactors existing code moving assembler functions for RVV into feature-specific files.
> 
> Hotspot and jdk tier1 passed on the unmatched board. Performed full jtreg tests with qemu without new failures.

Looks good. Thanks.

-------------

Marked as reviewed by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/32

From fyang at openjdk.java.net  Thu Dec 16 01:30:54 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Thu, 16 Dec 2021 01:30:54 GMT
Subject: git: openjdk/riscv-port: riscv-port: 8278547: riscv: Refactor moving
 assembler functions for vector instructions into separate file
Message-ID: <b919bff9-7f5e-4103-b5fd-0edc7537ab1f@openjdk.org>

Changeset: ec881ea7
Author:    Yanhong Zhu <yzhu at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
Date:      2021-12-16 01:30:30 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ec881ea794451181a124a0f57fcfab5349f7bdde

8278547: riscv: Refactor moving assembler functions for vector instructions into separate file

Reviewed-by: yadongwang, fyang

! src/hotspot/cpu/riscv/assembler_riscv.hpp
+ src/hotspot/cpu/riscv/assembler_riscv_v.hpp
! src/hotspot/cpu/riscv/riscv.ad


From yzhu at openjdk.java.net  Thu Dec 16 01:34:29 2021
From: yzhu at openjdk.java.net (Yanhong Zhu)
Date: Thu, 16 Dec 2021 01:34:29 GMT
Subject: [riscv-port] Integrated: 8278547: riscv: Refactor moving assembler
 functions for vector instructions into separate file
In-Reply-To: <IV91utXqA6lhy--_IyrjK7qSWDjXdatNZeZWROGJ8iE=.68dec187-e575-4396-b104-7d5f9192a376@github.com>
References: <IV91utXqA6lhy--_IyrjK7qSWDjXdatNZeZWROGJ8iE=.68dec187-e575-4396-b104-7d5f9192a376@github.com>
Message-ID: <gyDIQnLu_oyOqpM6vo2RPjvu3w4NA6qSx6JVB6iBn6M=.cefc89e4-ae86-47c6-a1cd-5e2a62f83432@github.com>

On Wed, 15 Dec 2021 08:59:57 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

> RISCV have several feature extensions: RVV, RVC and RVB.
> Work in under progress to support those features in Hotspot JVM.
> For maintenance purposes, we should move assembler functions for specific feature into separate file.
> This patch refactors existing code moving assembler functions for RVV into feature-specific files.
> 
> Hotspot and jdk tier1 passed on the unmatched board. Performed full jtreg tests with qemu without new failures.

This pull request has now been integrated.

Changeset: ec881ea7
Author:    Yanhong Zhu <yzhu at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/ec881ea794451181a124a0f57fcfab5349f7bdde
Stats:     1349 lines in 3 files changed: 696 ins; 651 del; 2 mod

8278547: riscv: Refactor moving assembler functions for vector instructions into separate file

Reviewed-by: yadongwang, fyang

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/32

From xlinzheng at openjdk.java.net  Thu Dec 16 01:44:28 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Thu, 16 Dec 2021 01:44:28 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers [v2]
In-Reply-To: <aw8hZHTcYN0d8DfdgsZQQQbvzgk_QtQjxUYHyNHB-J0=.d8f2b421-1f42-4e73-bb72-ebcb7aa734c0@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
 <-vouM1s0vp_lvBfu85ssS9NLQnraflUwJe8l13-yj-M=.ab053efc-e656-46e4-9d7b-1fec6f7382ad@github.com>
 <aw8hZHTcYN0d8DfdgsZQQQbvzgk_QtQjxUYHyNHB-J0=.d8f2b421-1f42-4e73-bb72-ebcb7aa734c0@github.com>
Message-ID: <UC_WkIVk0jNhgVXqbS7Nv1MNzfJED1S22v4geGcVtaM=.7a5e0846-8d70-408c-b19b-7ad32c42f56f@github.com>

On Thu, 16 Dec 2021 01:17:40 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Fix comments for JDK-8278337 and commit other improvements as proposed
>
> src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp line 337:
> 
>> 335:   // if the number of popped regs is odd, the reserved slot for alignment will be removed
>> 336:   // integer registers except ra(x1) & sp(x2) & gp(x3) & tp(x4) & x10
>> 337:   __ pop_reg(RegSet::range(x5, x9), sp);   // pop zr, x5 ~ x9
> 
> Is `zr` will be poped?

Currently it seems not: it looks like [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25) only removes the zr saving and restoring logic, but just remains that stack slot originally for zr unchanged.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/31

From fjiang at openjdk.java.net  Thu Dec 16 01:52:25 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Thu, 16 Dec 2021 01:52:25 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers [v2]
In-Reply-To: <UC_WkIVk0jNhgVXqbS7Nv1MNzfJED1S22v4geGcVtaM=.7a5e0846-8d70-408c-b19b-7ad32c42f56f@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
 <-vouM1s0vp_lvBfu85ssS9NLQnraflUwJe8l13-yj-M=.ab053efc-e656-46e4-9d7b-1fec6f7382ad@github.com>
 <aw8hZHTcYN0d8DfdgsZQQQbvzgk_QtQjxUYHyNHB-J0=.d8f2b421-1f42-4e73-bb72-ebcb7aa734c0@github.com>
 <UC_WkIVk0jNhgVXqbS7Nv1MNzfJED1S22v4geGcVtaM=.7a5e0846-8d70-408c-b19b-7ad32c42f56f@github.com>
Message-ID: <MAwt-nrnXMfkeUG_awZQMsDaDd1psNUHCh6uG-E1qBM=.aba9b273-b686-4ef4-b4a2-6e2eefdadbaf@github.com>

On Thu, 16 Dec 2021 01:40:38 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp line 337:
>> 
>>> 335:   // if the number of popped regs is odd, the reserved slot for alignment will be removed
>>> 336:   // integer registers except ra(x1) & sp(x2) & gp(x3) & tp(x4) & x10
>>> 337:   __ pop_reg(RegSet::range(x5, x9), sp);   // pop zr, x5 ~ x9
>> 
>> Is `zr` will be poped?
>
> Currently it seems not: it looks like [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25) only removes the zr saving and restoring logic, but just remains that stack slot originally for zr unchanged.

comment should be updated too though.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/31

From xlinzheng at openjdk.java.net  Thu Dec 16 03:06:42 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Thu, 16 Dec 2021 03:06:42 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers [v3]
In-Reply-To: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
Message-ID: <ith4AkR1i8VsYRcE71e39Bmcw_hqfjY-WJOZRkSgNiU=.3a8f8223-8c30-4591-8ea7-ce887674c7a9@github.com>

> Hi team,
> 
> x3 is the global pointer register used to reference global variables in C++ code, generated by linker; and x4 is the thread pointer register and would be modified by the kernel. In the riscv-port repo, we have no other modifications for the x3 & x4 registers so I would recommend removing the x3 & x4 saving logic in register savers. Previously verified along with other patches under full tiers jdk/hotspot on boards, and verified a simple `test/jtreg/hotspot/compiler` after fixing conflicts with [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25).
> 
> BTW since we remove both two registers together, sp remains 16-byte aligned without other changes in stack frames.
> 
> Thanks,
> Xiaolin

Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:

  Further fix comments for JDK-8278337

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/31/files
  - new: https://git.openjdk.java.net/riscv-port/pull/31/files/bdb5fba3..39d4e755

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=31&range=02
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=31&range=01-02

  Stats: 4 lines in 1 file changed: 0 ins; 0 del; 4 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/31.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/31/head:pull/31

PR: https://git.openjdk.java.net/riscv-port/pull/31

From xlinzheng at openjdk.java.net  Thu Dec 16 03:06:43 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Thu, 16 Dec 2021 03:06:43 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers [v2]
In-Reply-To: <MAwt-nrnXMfkeUG_awZQMsDaDd1psNUHCh6uG-E1qBM=.aba9b273-b686-4ef4-b4a2-6e2eefdadbaf@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
 <-vouM1s0vp_lvBfu85ssS9NLQnraflUwJe8l13-yj-M=.ab053efc-e656-46e4-9d7b-1fec6f7382ad@github.com>
 <aw8hZHTcYN0d8DfdgsZQQQbvzgk_QtQjxUYHyNHB-J0=.d8f2b421-1f42-4e73-bb72-ebcb7aa734c0@github.com>
 <UC_WkIVk0jNhgVXqbS7Nv1MNzfJED1S22v4geGcVtaM=.7a5e0846-8d70-408c-b19b-7ad32c42f56f@github.com>
 <MAwt-nrnXMfkeUG_awZQMsDaDd1psNUHCh6uG-E1qBM=.aba9b273-b686-4ef4-b4a2-6e2eefdadbaf@github.com>
Message-ID: <_cahrlC1feuAw1YeLsBZz92nJmsKNRcdQsOFR4GnjVs=.cc8d9a0c-4ead-4b1d-8aad-d7f3252f9769@github.com>

On Thu, 16 Dec 2021 01:49:25 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> Currently it seems not: it looks like [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25) only removes the zr saving and restoring logic, but just remains that stack slot originally for zr unchanged.
>
> comment should be updated too though.

Thanks for pointing it out -- seems there are unfixed comments at large out of my sight. I have fixed them according to the assembly code.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/31

From fjiang at openjdk.java.net  Thu Dec 16 03:40:27 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Thu, 16 Dec 2021 03:40:27 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers [v3]
In-Reply-To: <ith4AkR1i8VsYRcE71e39Bmcw_hqfjY-WJOZRkSgNiU=.3a8f8223-8c30-4591-8ea7-ce887674c7a9@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
 <ith4AkR1i8VsYRcE71e39Bmcw_hqfjY-WJOZRkSgNiU=.3a8f8223-8c30-4591-8ea7-ce887674c7a9@github.com>
Message-ID: <zzvVDzswhV1dqf5SX9y8ikGtYC1FfXymygJdtDSNhig=.5db7bfc1-ce3d-4f24-a924-6dc04c10b83c@github.com>

On Thu, 16 Dec 2021 03:06:42 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> Hi team,
>> 
>> x3 is the global pointer register used to reference global variables in C++ code, generated by linker; and x4 is the thread pointer register and would be modified by the kernel. In the riscv-port repo, we have no other modifications for the x3 & x4 registers so I would recommend removing the x3 & x4 saving logic in register savers. Previously verified along with other patches under full tiers jdk/hotspot on boards, and verified a simple `test/jtreg/hotspot/compiler` after fixing conflicts with [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25).
>> 
>> BTW since we remove both two registers together, sp remains 16-byte aligned without other changes in stack frames.
>> 
>> Thanks,
>> Xiaolin
>
> Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Further fix comments for JDK-8278337

Marked as reviewed by fjiang (Author).

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/31

From fjiang at openjdk.java.net  Thu Dec 16 03:59:15 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Thu, 16 Dec 2021 03:59:15 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers [v3]
In-Reply-To: <ith4AkR1i8VsYRcE71e39Bmcw_hqfjY-WJOZRkSgNiU=.3a8f8223-8c30-4591-8ea7-ce887674c7a9@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
 <ith4AkR1i8VsYRcE71e39Bmcw_hqfjY-WJOZRkSgNiU=.3a8f8223-8c30-4591-8ea7-ce887674c7a9@github.com>
Message-ID: <Ipwkp5Jgo3EIQ6mYGh0_hXjTydMT7i9GDBHBu5V3KNg=.1fb8c97f-a605-4e31-9906-7f5513ef3f0d@github.com>

On Thu, 16 Dec 2021 03:06:42 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> Hi team,
>> 
>> x3 is the global pointer register used to reference global variables in C++ code, generated by linker; and x4 is the thread pointer register and would be modified by the kernel. In the riscv-port repo, we have no other modifications for the x3 & x4 registers so I would recommend removing the x3 & x4 saving logic in register savers. Previously verified along with other patches under full tiers jdk/hotspot on boards, and verified a simple `test/jtreg/hotspot/compiler` after fixing conflicts with [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25).
>> 
>> BTW since we remove both two registers together, sp remains 16-byte aligned without other changes in stack frames.
>> 
>> Thanks,
>> Xiaolin
>
> Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Further fix comments for JDK-8278337

LGTM

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/31

From fyang at openjdk.java.net  Thu Dec 16 08:04:16 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Thu, 16 Dec 2021 08:04:16 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers [v3]
In-Reply-To: <ith4AkR1i8VsYRcE71e39Bmcw_hqfjY-WJOZRkSgNiU=.3a8f8223-8c30-4591-8ea7-ce887674c7a9@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
 <ith4AkR1i8VsYRcE71e39Bmcw_hqfjY-WJOZRkSgNiU=.3a8f8223-8c30-4591-8ea7-ce887674c7a9@github.com>
Message-ID: <u92QgO0oOK56SRIa9rex4vBKNQrA88DxY-XS5TYyWYM=.0b5baffe-09f4-46ab-999f-4602032c3ca2@github.com>

On Thu, 16 Dec 2021 03:06:42 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> Hi team,
>> 
>> x3 is the global pointer register used to reference global variables in C++ code, generated by linker; and x4 is the thread pointer register and would be modified by the kernel. In the riscv-port repo, we have no other modifications for the x3 & x4 registers so I would recommend removing the x3 & x4 saving logic in register savers. Previously verified along with other patches under full tiers jdk/hotspot on boards, and verified a simple `test/jtreg/hotspot/compiler` after fixing conflicts with [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25).
>> 
>> BTW since we remove both two registers together, sp remains 16-byte aligned without other changes in stack frames.
>> 
>> Thanks,
>> Xiaolin
>
> Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Further fix comments for JDK-8278337

Marked as reviewed by fyang (Lead).

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/31

From xlinzheng at openjdk.java.net  Thu Dec 16 08:07:26 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Thu, 16 Dec 2021 08:07:26 GMT
Subject: [riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers [v3]
In-Reply-To: <ith4AkR1i8VsYRcE71e39Bmcw_hqfjY-WJOZRkSgNiU=.3a8f8223-8c30-4591-8ea7-ce887674c7a9@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
 <ith4AkR1i8VsYRcE71e39Bmcw_hqfjY-WJOZRkSgNiU=.3a8f8223-8c30-4591-8ea7-ce887674c7a9@github.com>
Message-ID: <PMSUjxa9er37VOXK__UhRRVb7rd-KiWc-SrJk7LA4hE=.41175be7-9625-4615-89b3-5c1c39dcdc2d@github.com>

On Thu, 16 Dec 2021 03:06:42 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> Hi team,
>> 
>> x3 is the global pointer register used to reference global variables in C++ code, generated by linker; and x4 is the thread pointer register and would be modified by the kernel. In the riscv-port repo, we have no other modifications for the x3 & x4 registers so I would recommend removing the x3 & x4 saving logic in register savers. Previously verified along with other patches under full tiers jdk/hotspot on boards, and verified a simple `test/jtreg/hotspot/compiler` after fixing conflicts with [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25).
>> 
>> BTW since we remove both two registers together, sp remains 16-byte aligned without other changes in stack frames.
>> 
>> Thanks,
>> Xiaolin
>
> Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Further fix comments for JDK-8278337

Thanks for the reviews, team.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/31

From xlinzheng at openjdk.java.net  Thu Dec 16 08:11:17 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Thu, 16 Dec 2021 08:11:17 GMT
Subject: [riscv-port] Integrated: 8278833: riscv: Remove the x3 and x4 register
 saving logic in register savers
In-Reply-To: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
References: <ZXxlueiq4SoTQZDm5j68xFdCQ_NRftb-hzVFu6Y2Ldw=.6ca626b1-a3ec-4e3f-b3d4-9a05a9b6c4c1@github.com>
Message-ID: <hzbjYGqNUXu32HUQTxEQ5gkCq_xBkLBraVjRDemMHP8=.a676bb5c-846c-4d74-ae25-32d60fc527e9@github.com>

On Wed, 15 Dec 2021 02:59:37 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
> 
> x3 is the global pointer register used to reference global variables in C++ code, generated by linker; and x4 is the thread pointer register and would be modified by the kernel. In the riscv-port repo, we have no other modifications for the x3 & x4 registers so I would recommend removing the x3 & x4 saving logic in register savers. Previously verified along with other patches under full tiers jdk/hotspot on boards, and verified a simple `test/jtreg/hotspot/compiler` after fixing conflicts with [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25).
> 
> BTW since we remove both two registers together, sp remains 16-byte aligned without other changes in stack frames.
> 
> Thanks,
> Xiaolin

This pull request has now been integrated.

Changeset: 77902053
Author:    Xiaolin Zheng <xlinzheng at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/7790205306d21cfe080ed057ee07ccf98c86c87e
Stats:     40 lines in 3 files changed: 5 ins; 3 del; 32 mod

8278833: riscv: Remove the x3 and x4 register saving logic in register savers

Reviewed-by: yadongwang, fjiang, fyang

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/31

From duke at openjdk.java.net  Thu Dec 16 08:46:06 2021
From: duke at openjdk.java.net (duke)
Date: Thu, 16 Dec 2021 08:46:06 GMT
Subject: git: openjdk/riscv-port: riscv-port: 65 new changesets
Message-ID: <2684cc25-3dd3-4a1f-8977-3d7f4a0687db@openjdk.java.net>

Changeset: 0113322a
Author:    Jatin Bhateja <jbhateja at openjdk.org>
Date:      2021-12-10 01:49:20 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/0113322ac15e2441def3dec599199b98cbd02961

8277997: Intrinsic creation for VectorMask.fromLong API

Reviewed-by: psandoz, kvn, sviswanathan

! src/hotspot/cpu/x86/assembler_x86.cpp
! src/hotspot/cpu/x86/assembler_x86.hpp
! src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp
! src/hotspot/cpu/x86/c2_MacroAssembler_x86.hpp
! src/hotspot/cpu/x86/x86.ad
! src/hotspot/share/adlc/formssel.cpp
! src/hotspot/share/classfile/vmIntrinsics.hpp
! src/hotspot/share/opto/c2compiler.cpp
! src/hotspot/share/opto/classes.hpp
! src/hotspot/share/opto/library_call.cpp
! src/hotspot/share/opto/library_call.hpp
! src/hotspot/share/opto/vectorIntrinsics.cpp
! src/hotspot/share/opto/vectornode.cpp
! src/hotspot/share/opto/vectornode.hpp
! src/hotspot/share/prims/vectorSupport.hpp
! src/java.base/share/classes/jdk/internal/vm/vector/VectorSupport.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Byte128Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Byte256Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Byte512Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Byte64Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/ByteMaxVector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/ByteVector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Double128Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Double256Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Double512Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Double64Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/DoubleMaxVector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/DoubleVector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Float128Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Float256Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Float512Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Float64Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/FloatMaxVector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/FloatVector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Int128Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Int256Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Int512Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Int64Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/IntMaxVector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/IntVector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Long128Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Long256Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Long512Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Long64Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/LongMaxVector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/LongVector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Short128Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Short256Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Short512Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/Short64Vector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/ShortMaxVector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/ShortVector.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/VectorMask.java
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/X-Vector.java.template
! src/jdk.incubator.vector/share/classes/jdk/incubator/vector/X-VectorBits.java.template
! test/jdk/jdk/incubator/vector/Byte128VectorTests.java
! test/jdk/jdk/incubator/vector/Byte256VectorTests.java
! test/jdk/jdk/incubator/vector/Byte512VectorTests.java
! test/jdk/jdk/incubator/vector/Byte64VectorTests.java
! test/jdk/jdk/incubator/vector/Double128VectorTests.java
! test/jdk/jdk/incubator/vector/Double256VectorTests.java
! test/jdk/jdk/incubator/vector/Double512VectorTests.java
! test/jdk/jdk/incubator/vector/Double64VectorTests.java
! test/jdk/jdk/incubator/vector/Float128VectorTests.java
! test/jdk/jdk/incubator/vector/Float256VectorTests.java
! test/jdk/jdk/incubator/vector/Float512VectorTests.java
! test/jdk/jdk/incubator/vector/Float64VectorTests.java
! test/jdk/jdk/incubator/vector/Int128VectorTests.java
! test/jdk/jdk/incubator/vector/Int256VectorTests.java
! test/jdk/jdk/incubator/vector/Int512VectorTests.java
! test/jdk/jdk/incubator/vector/Int64VectorTests.java
! test/jdk/jdk/incubator/vector/Long128VectorTests.java
! test/jdk/jdk/incubator/vector/Long256VectorTests.java
! test/jdk/jdk/incubator/vector/Long512VectorTests.java
! test/jdk/jdk/incubator/vector/Long64VectorTests.java
! test/jdk/jdk/incubator/vector/Short128VectorTests.java
! test/jdk/jdk/incubator/vector/Short256VectorTests.java
! test/jdk/jdk/incubator/vector/Short512VectorTests.java
! test/jdk/jdk/incubator/vector/Short64VectorTests.java
! test/jdk/jdk/incubator/vector/templates/Unit-Miscellaneous.template
+ test/micro/org/openjdk/bench/jdk/incubator/vector/MaskFromLongBenchmark.java

Changeset: 539fbbf8
Author:    Hamlin Li <mli at openjdk.org>
Date:      2021-12-10 06:06:12 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/539fbbf8c7c6003af33fe148bc3ceb4e69966143

8278532: Fix some typos in compiler comments

Reviewed-by: kvn, jiefu

! src/hotspot/share/c1/c1_FrameMap.hpp
! src/hotspot/share/c1/c1_GraphBuilder.cpp
! src/hotspot/share/c1/c1_ValueMap.cpp
! src/hotspot/share/opto/phaseX.hpp

Changeset: aed3ea20
Author:    Jan Lahoda <jlahoda at openjdk.org>
Date:      2021-12-10 09:01:58 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/aed3ea2043e765bf4a9ac980da2515f19855c780

8277634: Incorrect method name in invokedynamic

Reviewed-by: jlaskey

! src/jdk.compiler/share/classes/com/sun/tools/javac/code/Symbol.java
! src/jdk.compiler/share/classes/com/sun/tools/javac/jvm/PoolConstant.java
+ test/langtools/tools/javac/classwriter/IndyCorrectInvocationName.java

Changeset: 3e0b083f
Author:    Hamlin Li <mli at openjdk.org>
Date:      2021-12-10 14:51:27 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3e0b083f2013f07b090af92a78c9a5f46f9fe427

8278533: Remove some unused methods in c1_Instruction and c1_ValueMap

Reviewed-by: chagedorn

! src/hotspot/share/c1/c1_Instruction.cpp
! src/hotspot/share/c1/c1_Instruction.hpp
! src/hotspot/share/c1/c1_ValueMap.hpp

Changeset: 8eb453ba
Author:    Roman Kennke <rkennke at openjdk.org>
Date:      2021-12-10 16:24:16 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8eb453baebe377697286f7eb32280ca9f1fd7775

8277072: ObjectStreamClass caches keep ClassLoaders alive

Reviewed-by: rriggs, plevart

+ src/java.base/share/classes/java/io/ClassCache.java
! src/java.base/share/classes/java/io/ObjectStreamClass.java
+ test/jdk/java/io/ObjectStreamClass/ObjectStreamClassCaching.java
+ test/jdk/java/io/ObjectStreamClass/TestOSCClassLoaderLeak.java

Changeset: 4f594e6a
Author:    Dan Lutker <lutkerd at amazon.com>
Committer: Paul Hohensee <phh at openjdk.org>
Date:      2021-12-10 17:52:54 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/4f594e6a28ad85d46d3252fb960f1c116f414899

8278381: [GCC 11] Address::make_raw() does not initialize rspec

Reviewed-by: phh, xliu

! src/hotspot/cpu/arm/assembler_arm_32.cpp
! src/hotspot/cpu/x86/assembler_x86.cpp

Changeset: afd065b3
Author:    Evgeny Astigeevich <eastig at amazon.com>
Committer: Paul Hohensee <phh at openjdk.org>
Date:      2021-12-10 18:27:36 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/afd065b3684f7b87563961c2b7a6ee6a354dbdf9

8278415: [TESTBUG] vmTestbase/nsk/stress/stack/stack018.java fails with "java.lang.Error: TEST_RFE"

Reviewed-by: phh

! test/hotspot/jtreg/vmTestbase/nsk/stress/stack/stack018.java

Changeset: ed5d53ae
Author:    Jonathan Gibbons <jjg at openjdk.org>
Date:      2021-12-10 02:50:37 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ed5d53ae0eb0b12de11fb3d79ae0371c093ce434

8273179: Update nroff pages in JDK 18 before RC

Reviewed-by: dholmes

! src/java.base/share/man/java.1
! src/java.base/share/man/keytool.1
! src/java.rmi/share/man/rmiregistry.1
! src/java.scripting/share/man/jrunscript.1
! src/jdk.compiler/share/man/javac.1
! src/jdk.compiler/share/man/serialver.1
! src/jdk.hotspot.agent/share/man/jhsdb.1
! src/jdk.httpserver/share/man/jwebserver.1
! src/jdk.jartool/share/man/jar.1
! src/jdk.jartool/share/man/jarsigner.1
! src/jdk.javadoc/share/man/javadoc.1
! src/jdk.jcmd/share/man/jcmd.1
! src/jdk.jcmd/share/man/jinfo.1
! src/jdk.jcmd/share/man/jmap.1
! src/jdk.jcmd/share/man/jps.1
! src/jdk.jcmd/share/man/jstack.1
! src/jdk.jcmd/share/man/jstat.1
! src/jdk.jconsole/share/man/jconsole.1
! src/jdk.jdeps/share/man/javap.1
! src/jdk.jdeps/share/man/jdeprscan.1
! src/jdk.jdeps/share/man/jdeps.1
! src/jdk.jdi/share/man/jdb.1
! src/jdk.jfr/share/man/jfr.1
! src/jdk.jlink/share/man/jlink.1
! src/jdk.jlink/share/man/jmod.1
! src/jdk.jpackage/share/man/jpackage.1
! src/jdk.jshell/share/man/jshell.1
! src/jdk.jstatd/share/man/jstatd.1

Changeset: 3df8dc49
Author:    Jonathan Gibbons <jjg at openjdk.org>
Date:      2021-12-10 05:02:28 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3df8dc494d2d0e6d1003094c9e129be2cca10a3c

8278538: Test langtools/jdk/javadoc/tool/CheckManPageOptions.java fails after the manpage was updated

Reviewed-by: dholmes

! test/langtools/jdk/javadoc/tool/CheckManPageOptions.java

Changeset: 0602f4c4
Author:    Hao Sun <haosun at openjdk.org>
Committer: Aleksey Shipilev <shade at openjdk.org>
Date:      2021-12-10 15:53:27 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/0602f4c48b0ffe53a6081551988b417d7536efa0

8277621: ARM32: multiple fastdebug failures with "bad AD file" after JDK-8276162

Reviewed-by: njian, dlong, shade

! src/hotspot/cpu/arm/arm.ad

Changeset: 61736f81
Author:    Jesper Wilhelmsson <jwilhelm at openjdk.org>
Date:      2021-12-10 18:42:51 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/61736f81fb4a20375c83d59e2b37a00aafb11107

Merge


Changeset: 81c56c70
Author:    Phil Race <prr at openjdk.org>
Date:      2021-12-10 21:02:28 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/81c56c700a47c7f1b7855052de17eb88fac84674

8278456: Define jtreg jdk_desktop test group time-based sub-tasks for use by headful testing.

Reviewed-by: serb, aivanov, psadhukhan

! test/jdk/TEST.groups

Changeset: 6eb6ec05
Author:    Dan Lutker <lutkerd at amazon.com>
Committer: Paul Hohensee <phh at openjdk.org>
Date:      2021-12-10 23:49:41 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/6eb6ec05fd4f80e11d0b052b58190bc8b53f4b11

8278525: Additional -Wnonnull errors happen with GCC 11

Reviewed-by: phh, dlong

! src/hotspot/cpu/x86/assembler_x86.cpp

Changeset: db68a0ce
Author:    Andrew Leonard <aleonard at openjdk.org>
Date:      2021-12-11 15:27:08 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/db68a0ce1ce152345320e70acb7e9842d2f1ece4

8276766: Enable jar and jmod to produce deterministic timestamped content

Reviewed-by: ihse, lancea, alanb, jgneff

! src/jdk.jartool/share/classes/sun/tools/jar/GNUStyleOptions.java
! src/jdk.jartool/share/classes/sun/tools/jar/Main.java
! src/jdk.jartool/share/classes/sun/tools/jar/resources/jar.properties
! src/jdk.jlink/share/classes/jdk/tools/jmod/JmodOutputStream.java
! src/jdk.jlink/share/classes/jdk/tools/jmod/JmodTask.java
! src/jdk.jlink/share/classes/jdk/tools/jmod/resources/jmod.properties
+ test/jdk/tools/jar/ReproducibleJar.java
! test/jdk/tools/jmod/JmodTest.java

Changeset: 7c2c5858
Author:    Sergey Bylokhov <serb at openjdk.org>
Date:      2021-12-12 21:47:03 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/7c2c58587d4eda5523331eae45e7d897252dc097

8276819: javax/print/PrintServiceLookup/FlushCustomClassLoader.java fails to free

Reviewed-by: psadhukhan, aivanov

! test/jdk/javax/print/PrintServiceLookup/FlushCustomClassLoader.java

Changeset: 8b5ff4bd
Author:    Matthias Baesken <mbaesken at openjdk.org>
Date:      2021-12-13 07:48:20 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8b5ff4bdffc8f32317d67b00c085071d6c772b30

8278344: sun/security/pkcs12/KeytoolOpensslInteropTest.java test fails because of different openssl output

Reviewed-by: mdoerr, goetz, stuefe

! test/jdk/sun/security/pkcs12/KeytoolOpensslInteropTest.java

Changeset: ccdb9f1b
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-12-13 09:50:30 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ccdb9f1b160a0f49ee86c7a2714d2381d68419cc

8278482: G1: Improve HeapRegion::block_is_obj

Reviewed-by: sjohanss, tschatzl, mli

! src/hotspot/share/gc/g1/heapRegion.cpp
! src/hotspot/share/gc/g1/heapRegion.inline.hpp

Changeset: 23fd9f15
Author:    Christian Stein <cstein at openjdk.org>
Committer: Lance Andersen <lancea at openjdk.org>
Date:      2021-12-13 12:00:47 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/23fd9f15da40cef00231380766158bc0fa537c38

8271079: JavaFileObject#toUri and multi-release jars

Reviewed-by: jjg, lancea, alanb

! src/jdk.compiler/share/classes/com/sun/tools/javac/file/PathFileObject.java
! src/jdk.zipfs/share/classes/jdk/nio/zipfs/ZipFileSystem.java
! src/jdk.zipfs/share/classes/jdk/nio/zipfs/ZipPath.java
! test/jdk/jdk/nio/zipfs/ZipFSTester.java
! test/jdk/jdk/nio/zipfs/jarfs/JFSTester.java
+ test/langtools/tools/javac/T8271079.java

Changeset: 14f7385a
Author:    Harold Seigel <hseigel at openjdk.org>
Date:      2021-12-13 13:35:37 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/14f7385a72972e1f15b3103cc75a60c5733f6d98

8277481: Obsolete seldom used CDS flags

Reviewed-by: iklam, ccheung, dholmes

! src/hotspot/share/runtime/arguments.cpp
! src/hotspot/share/runtime/globals.hpp
! src/hotspot/share/utilities/globalDefinitions.cpp
! src/hotspot/share/utilities/globalDefinitions.hpp
! src/java.base/share/classes/jdk/internal/misc/CDS.java
! src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/VM.java
! src/jdk.hotspot.agent/share/native/libsaproc/ps_core_common.c
! test/hotspot/jtreg/runtime/cds/SharedArchiveFile.java
! test/hotspot/jtreg/runtime/cds/appcds/dynamicArchive/DynamicArchiveTestBase.java
- test/hotspot/jtreg/runtime/cds/appcds/dynamicArchive/DynamicFlag.java
! test/hotspot/jtreg/runtime/cds/appcds/jcmd/JCmdTestDumpBase.java
! test/hotspot/jtreg/runtime/cds/appcds/jcmd/JCmdTestDynamicDump.java
! test/hotspot/jtreg/runtime/cds/appcds/jcmd/JCmdTestStaticDump.java

Changeset: 15996e40
Author:    Harold Seigel <hseigel at openjdk.org>
Date:      2021-12-13 13:40:54 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/15996e407563eda844266f1cbcdc20be74b4b4e4

8276241: JVM does not flag constant class entries ending in '/'

Reviewed-by: dholmes, lfoltan

! src/hotspot/share/classfile/classFileParser.cpp
+ test/hotspot/jtreg/runtime/classFileParserBug/TrailingSlashTest.java

Changeset: ca8c58c7
Author:    merykitty <anhmdq99 at gmail.com>
Committer: Paul Sandoz <psandoz at openjdk.org>
Date:      2021-12-13 16:34:37 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ca8c58c731959e3a1b8fe02255ed44fc1d14d565

8259610: VectorReshapeTests are not effective due to failing to intrinsify "VectorSupport.convert"

Reviewed-by: psandoz, chagedorn

! test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java
+ test/hotspot/jtreg/compiler/vectorapi/reshape/TestVectorCastAVX1.java
+ test/hotspot/jtreg/compiler/vectorapi/reshape/TestVectorCastAVX2.java
+ test/hotspot/jtreg/compiler/vectorapi/reshape/TestVectorCastAVX512.java
+ test/hotspot/jtreg/compiler/vectorapi/reshape/TestVectorCastAVX512DQ.java
+ test/hotspot/jtreg/compiler/vectorapi/reshape/TestVectorCastNeon.java
+ test/hotspot/jtreg/compiler/vectorapi/reshape/TestVectorCastSVE.java
+ test/hotspot/jtreg/compiler/vectorapi/reshape/TestVectorReinterpret.java
+ test/hotspot/jtreg/compiler/vectorapi/reshape/tests/TestVectorCast.java
+ test/hotspot/jtreg/compiler/vectorapi/reshape/tests/TestVectorDoubleExpandShrink.java
+ test/hotspot/jtreg/compiler/vectorapi/reshape/tests/TestVectorExpandShrink.java
+ test/hotspot/jtreg/compiler/vectorapi/reshape/tests/TestVectorRebracket.java
+ test/hotspot/jtreg/compiler/vectorapi/reshape/utils/TestCastMethods.java
+ test/hotspot/jtreg/compiler/vectorapi/reshape/utils/UnsafeUtils.java
+ test/hotspot/jtreg/compiler/vectorapi/reshape/utils/VectorReshapeHelper.java
+ test/hotspot/jtreg/compiler/vectorapi/reshape/utils/VectorSpeciesPair.java

Changeset: db502d30
Author:    Chris Plummer <cjplummer at openjdk.org>
Date:      2021-12-13 19:02:12 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/db502d30a42847f69273f48378f230d9d55eb8d6

8269556: sun/tools/jhsdb/JShellHeapDumpTest.java fails with RuntimeException 'JShellToolProvider' missing from stdout/stderr

Reviewed-by: kevinw, sspitsyn, amenkov

! test/jdk/sun/tools/jhsdb/JShellHeapDumpTest.java

Changeset: bdc784c0
Author:    Daniel D. Daugherty <dcubed at openjdk.org>
Date:      2021-12-13 20:36:40 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/bdc784c0cb02d76c6d3a1608a89f4b64f86253eb

8278630: ProblemList compiler/vectorapi/reshape/TestVectorCastAVX512.java on X64

Reviewed-by: psandoz

! test/hotspot/jtreg/ProblemList.txt

Changeset: 624f3094
Author:    David Holmes <dholmes at openjdk.org>
Date:      2021-12-13 21:36:24 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/624f3094b89976a0be0a1d1d4ce304f4be38fb9e

8278275: Initial nroff manpage generation for JDK 19

Reviewed-by: erikj, jjg, iris

! src/java.base/share/man/java.1
! src/java.base/share/man/keytool.1
! src/java.rmi/share/man/rmiregistry.1
! src/java.scripting/share/man/jrunscript.1
! src/jdk.compiler/share/man/javac.1
! src/jdk.compiler/share/man/serialver.1
! src/jdk.hotspot.agent/share/man/jhsdb.1
! src/jdk.httpserver/share/man/jwebserver.1
! src/jdk.jartool/share/man/jar.1
! src/jdk.jartool/share/man/jarsigner.1
! src/jdk.javadoc/share/man/javadoc.1
! src/jdk.jcmd/share/man/jcmd.1
! src/jdk.jcmd/share/man/jinfo.1
! src/jdk.jcmd/share/man/jmap.1
! src/jdk.jcmd/share/man/jps.1
! src/jdk.jcmd/share/man/jstack.1
! src/jdk.jcmd/share/man/jstat.1
! src/jdk.jconsole/share/man/jconsole.1
! src/jdk.jdeps/share/man/javap.1
! src/jdk.jdeps/share/man/jdeprscan.1
! src/jdk.jdeps/share/man/jdeps.1
! src/jdk.jdi/share/man/jdb.1
! src/jdk.jfr/share/man/jfr.1
! src/jdk.jlink/share/man/jlink.1
! src/jdk.jlink/share/man/jmod.1
! src/jdk.jpackage/share/man/jpackage.1
! src/jdk.jshell/share/man/jshell.1
! src/jdk.jstatd/share/man/jstatd.1

Changeset: 94127f43
Author:    Alexander Zuev <kizune at openjdk.org>
Date:      2021-12-10 20:27:07 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/94127f43a4a28a89094fa93cd1da49763134f9db

8277299: STACK_OVERFLOW in Java_sun_awt_shell_Win32ShellFolder2_getIconBits

Reviewed-by: aivanov

! src/java.desktop/windows/native/libawt/windows/ShellFolder2.cpp
+ test/jdk/javax/swing/JFileChooser/FileSystemView/ShellFolderStackOverflow.java

Changeset: 9b99cbe7
Author:    Daniel D. Daugherty <dcubed at openjdk.org>
Date:      2021-12-11 15:53:31 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/9b99cbe7abf56d3ad5231a68b6506e35b89133c9

8278580: ProblemList javax/swing/JTree/4908142/bug4908142.java on macosx-x64

Reviewed-by: alanb

! test/jdk/ProblemList.txt

Changeset: 9a1bbaf8
Author:    Scott Gibbons <scott.gibbons at intel.com>
Committer: Vladimir Kozlov <kvn at openjdk.org>
Date:      2021-12-12 16:08:35 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/9a1bbaf8db0e869ab76be8ab1bd0ddeb23693e7e

8273108: RunThese24H crashes with SEGV in markWord::displaced_mark_helper() after JDK-8268276
8272809: JFR thread sampler SI_KERNEL SEGV in metaspace::VirtualSpaceList::contains

Reviewed-by: sviswanathan, kvn

! src/hotspot/cpu/x86/stubGenerator_x86_64.cpp
! test/hotspot/jtreg/compiler/intrinsics/base64/TestBase64.java

Changeset: c93b24d8
Author:    David Holmes <dholmes at openjdk.org>
Date:      2021-12-13 21:37:51 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/c93b24d85289167639e9ec4b79bd85403687161b

8132785: java/lang/management/ThreadMXBean/ThreadLists.java fails intermittently

Reviewed-by: alanb, kevinw, dcubed, sspitsyn

! test/jdk/ProblemList.txt
! test/jdk/java/lang/management/ThreadMXBean/ThreadLists.java

Changeset: 8401a059
Author:    Jesper Wilhelmsson <jwilhelm at openjdk.org>
Date:      2021-12-14 02:15:15 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8401a059bd01b32e3532f806d3d8b60e851c468a

Merge


Changeset: 3f9638d1
Author:    Thomas Stuefe <stuefe at openjdk.org>
Date:      2021-12-14 05:45:56 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3f9638d124076019f49eb77bc3ff8b466e4beb53

8278585: Drop unused code from OSThread

Reviewed-by: dholmes, tschatzl

! src/hotspot/os/aix/osThread_aix.hpp
! src/hotspot/os/aix/os_aix.cpp
! src/hotspot/os/bsd/osThread_bsd.hpp
! src/hotspot/os/bsd/os_bsd.cpp
! src/hotspot/os/linux/osThread_linux.hpp
! src/hotspot/os/linux/os_linux.cpp
! src/hotspot/os/windows/osThread_windows.hpp
! src/hotspot/os/windows/os_windows.cpp
! src/hotspot/share/jfr/writers/jfrJavaEventWriter.cpp
! src/hotspot/share/runtime/osThread.cpp
! src/hotspot/share/runtime/osThread.hpp
! src/hotspot/share/runtime/thread.cpp

Changeset: 7761a3e8
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-12-14 17:11:11 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/7761a3e883bcd18b0b235248c37f9228fd37b927

8278761: Parallel: Remove unused PSOldPromotionLAB constructor

Reviewed-by: tschatzl

! src/hotspot/share/gc/parallel/psPromotionLAB.hpp

Changeset: 3f91948c
Author:    Coleen Phillimore <coleenp at openjdk.org>
Date:      2021-12-14 17:45:35 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3f91948c592d6968d2de6c59a5d93866f439c0e8

8278791: Rename ClassLoaderData::holder_phantom

Reviewed-by: stefank

! src/hotspot/share/cds/metaspaceShared.cpp
! src/hotspot/share/classfile/classLoaderData.cpp
! src/hotspot/share/classfile/classLoaderData.hpp
! src/hotspot/share/classfile/classLoaderDataGraph.cpp
! src/hotspot/share/oops/klass.inline.hpp

Changeset: a9c1acbb
Author:    Sergey Bylokhov <serb at openjdk.org>
Date:      2021-12-14 18:03:00 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/a9c1acbb8aec46e4a488b7c77bb6318af87747f6

8275843: Random crashes while the UI code is executed

Reviewed-by: azvegint

! src/java.desktop/unix/classes/sun/java2d/xr/XRCompositeManager.java
! src/java.desktop/unix/classes/sun/java2d/xr/XRGraphicsConfig.java
! src/java.desktop/unix/classes/sun/java2d/xr/XRSurfaceData.java
! test/jdk/java/awt/ColorClass/AlphaColorTest.java
! test/jdk/java/awt/ColorClass/XRenderTranslucentColorDrawTest.java
+ test/jdk/java/awt/image/ColorModel/DrawCustomColorModel.java

Changeset: de65230d
Author:    Zhengyu Gu <zgu at openjdk.org>
Date:      2021-12-14 18:39:28 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/de65230d7183eb2d534afae5891eaa27074b8a7d

8278767: Shenandoah: Remove unused ShenandoahRootScanner

Reviewed-by: rkennke

! src/hotspot/share/gc/shenandoah/shenandoahRootProcessor.cpp
! src/hotspot/share/gc/shenandoah/shenandoahRootProcessor.hpp

Changeset: a1dfe572
Author:    Vladimir Kozlov <kvn at openjdk.org>
Date:      2021-12-14 19:24:13 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/a1dfe57249db15c0c05d33a0014ac914a7093089

8276455: C2: iterative EA

Reviewed-by: iveresov, neliasso, roland

! src/hotspot/share/opto/c2compiler.cpp
! src/hotspot/share/opto/c2compiler.hpp
! src/hotspot/share/opto/compile.cpp
! src/hotspot/share/opto/compile.hpp
! src/hotspot/share/opto/escape.cpp
! src/hotspot/share/opto/escape.hpp
+ test/hotspot/jtreg/compiler/c2/irTests/TestIterativeEA.java
+ test/hotspot/jtreg/compiler/escapeAnalysis/TestIterativeEA.java
+ test/micro/org/openjdk/bench/vm/compiler/IterativeEA.java
+ test/micro/org/openjdk/bench/vm/compiler/PointerBenchmarkFlat.java

Changeset: 03f647f4
Author:    Roger Riggs <rriggs at openjdk.org>
Date:      2021-12-14 19:54:54 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/03f647f4bb640bf5df1c461eec9860c7ac3eb076

8278028: [test-library] Warnings cleanup of the test library

Reviewed-by: dfuchs, mchung, naoto, lancea, lmesnik

! test/lib-test/jdk/test/lib/AssertsTest.java
! test/lib-test/jdk/test/lib/TestPlatformIsTieredSupported.java
! test/lib-test/jdk/test/lib/format/ArrayDiffTest.java
! test/lib-test/jdk/test/whitebox/OldWhiteBox.java
! test/lib-test/jdk/test/whitebox/vm_flags/VmFlagTest.java
! test/lib/RedefineClassHelper.java
! test/lib/jdk/test/lib/NetworkConfiguration.java
! test/lib/jdk/test/lib/compiler/InMemoryJavaCompiler.java
! test/lib/jdk/test/lib/format/ArrayCodec.java
! test/lib/jdk/test/lib/format/ArrayDiff.java
! test/lib/jdk/test/lib/hexdump/ASN1Formatter.java
! test/lib/jdk/test/lib/hexdump/StreamDump.java
! test/lib/jdk/test/lib/process/Proc.java
! test/lib/jdk/test/lib/process/ProcessTools.java

Changeset: 98a8d446
Author:    Harold Seigel <hseigel at openjdk.org>
Date:      2021-12-14 20:35:49 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/98a8d446b69fd84355731a8a3192cbd42671abb8

8278638: Remove FLAG_IS_CMDLINE(UseSharedSpaces)

Reviewed-by: dcubed, coleenp

! src/hotspot/share/runtime/arguments.cpp

Changeset: 2def7e91
Author:    Jie Fu <jiefu at openjdk.org>
Date:      2021-12-14 22:49:04 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/2def7e913207af788e582ed5bde21b28883183de

8278584: compiler/vectorapi/VectorMaskLoadStoreTest.java failed with "Error: ShouldNotReachHere()"

Reviewed-by: kvn, psandoz

! src/hotspot/cpu/x86/x86.ad
! test/hotspot/jtreg/compiler/vectorapi/VectorMaskLoadStoreTest.java

Changeset: 068a4509
Author:    Liam Miller-Cushon <cushon at openjdk.org>
Date:      2021-12-15 00:26:17 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/068a450954530d9a469db05d7cf2e7dcf1eddc8a

8278825: Unused variable for diagnostic in Resolve

Reviewed-by: vromero

! src/jdk.compiler/share/classes/com/sun/tools/javac/comp/Resolve.java

Changeset: 54c9a996
Author:    Chris Plummer <cjplummer at openjdk.org>
Date:      2021-12-15 01:25:53 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/54c9a99663c47b0477392a606637986bc5c87464

8278643: CoreUtils.getCoreFileLocation() should print out the size of the core file found

Reviewed-by: amenkov, lmesnik, sspitsyn

! test/lib/jdk/test/lib/util/CoreUtils.java

Changeset: 46f99aca
Author:    Chris Plummer <cjplummer at openjdk.org>
Date:      2021-12-15 01:29:50 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/46f99aca94ed878a94878eacb113fe2813050ad7

8244765: Undo exclusiveAccess.dirs changes for JDK-8220295 and see if there are still any testing issues

Reviewed-by: amenkov, sspitsyn

! test/jdk/TEST.ROOT

Changeset: c442587f
Author:    Fei Gao <fgao at openjdk.org>
Committer: Pengfei Li <pli at openjdk.org>
Date:      2021-12-15 02:26:40 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/c442587f1e72a614302cd76c20e13f1cb1703641

8277619: AArch64: Incorrect parameter type in Advanced SIMD Copy assembler functions

Reviewed-by: aph, pli

! src/hotspot/cpu/aarch64/aarch64.ad
! src/hotspot/cpu/aarch64/aarch64_neon.ad
! src/hotspot/cpu/aarch64/aarch64_neon_ad.m4
! src/hotspot/cpu/aarch64/assembler_aarch64.hpp
! src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
! test/hotspot/gtest/aarch64/aarch64-asmtest.py
! test/hotspot/gtest/aarch64/asmtest.out.h

Changeset: 758fe9be
Author:    Chris Plummer <cjplummer at openjdk.org>
Date:      2021-12-15 03:11:27 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/758fe9bed3daf9a31d15291ef9787dc5a914451f

8273904: debug agent ArrayTypeImp::newInstance() fails to send reply packet if there is an error

Reviewed-by: sspitsyn, amenkov

! src/jdk.jdwp.agent/share/native/libjdwp/ArrayTypeImpl.c

Changeset: 7adf7f33
Author:    Per Liden <pliden at openjdk.org>
Date:      2021-12-15 10:09:02 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/7adf7f3353ab81c5af3f2fc4c0fc9e4cf8905e32

8278351: Add function to retrieve worker_id from any context

Reviewed-by: eosterlund, kbarrett, ayang

! src/hotspot/share/gc/shared/referenceProcessor.cpp
! src/hotspot/share/gc/shared/workerThread.cpp
! src/hotspot/share/gc/shared/workerThread.hpp
! src/hotspot/share/gc/shenandoah/shenandoahWorkGroup.cpp
! src/hotspot/share/gc/shenandoah/shenandoahWorkGroup.hpp

Changeset: 1e3ae3be
Author:    Coleen Phillimore <coleenp at openjdk.org>
Date:      2021-12-15 13:41:59 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/1e3ae3be02e1fa76c632ef289dd1887c7fa369ec

8202579: Revisit VM_Version and VM_Version_ext for overlap and consolidation

Reviewed-by: dholmes, hseigel

! src/hotspot/cpu/aarch64/vm_version_aarch64.cpp
! src/hotspot/cpu/aarch64/vm_version_aarch64.hpp
- src/hotspot/cpu/aarch64/vm_version_ext_aarch64.cpp
- src/hotspot/cpu/aarch64/vm_version_ext_aarch64.hpp
! src/hotspot/cpu/arm/vm_version_arm.hpp
! src/hotspot/cpu/arm/vm_version_arm_32.cpp
- src/hotspot/cpu/arm/vm_version_ext_arm.cpp
- src/hotspot/cpu/arm/vm_version_ext_arm.hpp
- src/hotspot/cpu/ppc/vm_version_ext_ppc.cpp
- src/hotspot/cpu/ppc/vm_version_ext_ppc.hpp
! src/hotspot/cpu/ppc/vm_version_ppc.cpp
! src/hotspot/cpu/ppc/vm_version_ppc.hpp
- src/hotspot/cpu/s390/vm_version_ext_s390.cpp
- src/hotspot/cpu/s390/vm_version_ext_s390.hpp
! src/hotspot/cpu/s390/vm_version_s390.cpp
! src/hotspot/cpu/s390/vm_version_s390.hpp
! src/hotspot/cpu/x86/rdtsc_x86.cpp
- src/hotspot/cpu/x86/vm_version_ext_x86.cpp
- src/hotspot/cpu/x86/vm_version_ext_x86.hpp
! src/hotspot/cpu/x86/vm_version_x86.cpp
! src/hotspot/cpu/x86/vm_version_x86.hpp
- src/hotspot/cpu/zero/vm_version_ext_zero.cpp
- src/hotspot/cpu/zero/vm_version_ext_zero.hpp
! src/hotspot/cpu/zero/vm_version_zero.cpp
! src/hotspot/cpu/zero/vm_version_zero.hpp
! src/hotspot/os/aix/os_perf_aix.cpp
! src/hotspot/os/bsd/os_perf_bsd.cpp
! src/hotspot/os/linux/os_perf_linux.cpp
! src/hotspot/os/windows/os_perf_windows.cpp
! src/hotspot/share/prims/jvm.cpp
! src/hotspot/share/prims/jvmtiExport.cpp
! src/hotspot/share/runtime/abstract_vm_version.cpp
! src/hotspot/share/runtime/abstract_vm_version.hpp

Changeset: 4851ad84
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-12-15 15:02:57 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/4851ad840a8c3b93f978b829f50a27a2f629fa82

8278548: G1: Remove unnecessary check in forward_to_block_containing_addr

Reviewed-by: tschatzl, mli, sjohanss

! src/hotspot/share/gc/g1/g1BlockOffsetTable.inline.hpp

Changeset: fcebe65c
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-12-15 15:04:11 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/fcebe65ce9dc177d9fa16db606e3c8c33b2f771a

8278842: Parallel: Remove unused VerifyObjectStartArrayClosure::_old_gen

Reviewed-by: tschatzl

! src/hotspot/share/gc/parallel/psOldGen.cpp

Changeset: bcb79fd0
Author:    Evgeny Astigeevich <eastig at amazon.com>
Committer: Paul Hohensee <phh at openjdk.org>
Date:      2021-12-15 16:57:30 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/bcb79fd012c9c298e58c20c59e564e9d2c16b970

8278241: Implement JVM SpinPause on linux-aarch64

Reviewed-by: aph, phh

! src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp
! src/hotspot/cpu/aarch64/stubRoutines_aarch64.cpp
! src/hotspot/cpu/aarch64/stubRoutines_aarch64.hpp
! src/hotspot/os_cpu/linux_aarch64/os_linux_aarch64.cpp
+ test/hotspot/jtreg/runtime/Thread/TestSpinPause.java

Changeset: 1f1db838
Author:    Weijun Wang <weijun at openjdk.org>
Date:      2021-12-15 17:00:55 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/1f1db838ab7d427170d59a8b55fdb45c4d80c359

8278186: org.jcp.xml.dsig.internal.dom.Utils.parseIdFromSameDocumentURI throws StringIndexOutOfBoundsException when calling substring method

Reviewed-by: mullan

! src/java.xml.crypto/share/classes/org/jcp/xml/dsig/internal/dom/DOMURIDereferencer.java
! src/java.xml.crypto/share/classes/org/jcp/xml/dsig/internal/dom/Utils.java
+ test/jdk/javax/xml/crypto/dsig/BadXPointer.java
! test/lib/jdk/test/lib/security/XMLUtils.java

Changeset: 7517c85d
Author:    Chris Plummer <cjplummer at openjdk.org>
Date:      2021-12-15 17:08:44 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/7517c85da3236e5274580645d4c3cdecb1db25c5

8269838: BasicTypeDataBase.findDynamicTypeForAddress(addr, basetype) can be simplified

Reviewed-by: kevinw, sspitsyn

! src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/types/basic/BasicTypeDataBase.java

Changeset: 04dbdd36
Author:    Andrey Turbanov <turbanoff at gmail.com>
Committer: Serguei Spitsyn <sspitsyn at openjdk.org>
Date:      2021-12-15 19:28:58 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/04dbdd36dd04bf40737cb8c2f13d5b75303d2b1a

8274898: Cleanup usages of StringBuffer in jdk tools modules

Reviewed-by: sspitsyn, lmesnik

! src/jdk.jartool/share/classes/sun/security/tools/jarsigner/Main.java
! src/jdk.jpackage/share/classes/jdk/jpackage/internal/Log.java
! src/jdk.jshell/share/classes/jdk/internal/jshell/tool/Feedback.java

Changeset: 4ba980ba
Author:    Ioi Lam <iklam at openjdk.org>
Date:      2021-12-15 20:06:56 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/4ba980ba439f94a6b5015e64382a6c308476d63f

8278020: ~13% variation in Renaissance-Scrabble

Reviewed-by: dholmes, stuefe, kvn

! src/hotspot/share/oops/klass.hpp

Changeset: 32139c1a
Author:    Dean Long <dlong at openjdk.org>
Date:      2021-12-14 03:16:17 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/32139c1a8aae51c0869f41be57580ff4463913d2

8262134: compiler/uncommontrap/TestDeoptOOM.java failed with "guarantee(false) failed: wrong number of expression stack elements during deopt"

Reviewed-by: kvn, iveresov

! src/hotspot/share/c1/c1_IR.cpp
! src/hotspot/share/c1/c1_IR.hpp
! src/hotspot/share/c1/c1_LIRAssembler.cpp
! src/hotspot/share/runtime/deoptimization.cpp
! test/hotspot/jtreg/runtime/BootstrapMethod/BSMCalledTwice.java

Changeset: 475ec8e6
Author:    Markus Gr?nlund <mgronlun at openjdk.org>
Date:      2021-12-14 13:00:39 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/475ec8e6c5abc3431344d69bd46395e8c4b46e4c

8277919: OldObjectSample event causing bloat in the class constant pool in JFR recording

Reviewed-by: jbachorik

! src/hotspot/share/jfr/leakprofiler/checkpoint/objectSampleCheckpoint.cpp
! src/hotspot/share/jfr/recorder/checkpoint/types/jfrTypeSet.cpp
! src/hotspot/share/jfr/recorder/checkpoint/types/jfrTypeSetUtils.hpp

Changeset: 0cc989b7
Author:    Weijun Wang <weijun at openjdk.org>
Date:      2021-12-14 18:39:22 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/0cc989b7d2fa3b903d71b7baab53b853455005ba

8278744: KeyStore:getAttributes() not returning unmodifiable Set

Reviewed-by: mullan

! src/java.base/share/classes/sun/security/pkcs12/PKCS12KeyStore.java
+ test/jdk/java/security/KeyStore/PKCS12/UnmodifiableAttributes.java

Changeset: f48a3e86
Author:    Jie Fu <jiefu at openjdk.org>
Date:      2021-12-14 22:50:21 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f48a3e86d0274912160f3c415f92741eefa1cb1d

8278758: runtime/BootstrapMethod/BSMCalledTwice.java fails with release VMs after JDK-8262134

Reviewed-by: dcubed

! test/hotspot/jtreg/runtime/BootstrapMethod/BSMCalledTwice.java

Changeset: 918e3397
Author:    Alexander Matveev <almatvee at openjdk.org>
Date:      2021-12-14 23:59:11 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/918e3397858c425e9c3b82c9a918b7626603a59c

8278233: [macos] tools/jpackage tests timeout due to /usr/bin/osascript

Reviewed-by: herrick, asemenyuk

! src/jdk.jpackage/share/classes/jdk/jpackage/internal/IOUtils.java
! test/jdk/ProblemList.txt

Changeset: d6b5544e
Author:    Maurizio Cimadamore <mcimadamore at openjdk.org>
Date:      2021-12-15 12:25:25 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/d6b5544e74d46c1ca464a1994e73ddd323ef5c2b

8278607: Misc issues in foreign API javadoc

Reviewed-by: sundar

! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/CLinker.java
! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/MemoryAddress.java
! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/MemorySegment.java
! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/SegmentAllocator.java
! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/VaList.java
! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/ValueLayout.java
! src/jdk.incubator.foreign/share/classes/jdk/incubator/foreign/package-info.java

Changeset: 69b5d49e
Author:    Erik Gahlin <egahlin at openjdk.org>
Date:      2021-12-15 13:24:04 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/69b5d49e4f3a6b1ea616c39815dd16530eb32887

8272064: test/jdk/jdk/jfr/api/consumer/TestHiddenMethod.java needs update for JEP 416

Reviewed-by: jbachorik

! test/jdk/jdk/jfr/api/consumer/TestHiddenMethod.java

Changeset: d3408a46
Author:    Vladimir Kozlov <kvn at openjdk.org>
Date:      2021-12-15 21:45:45 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/d3408a46b7c8c2f8b5e41f3e286a497064a2c104

8277964: ClassCastException with no stack trace is thrown with -Xcomp in method handle invocation

Reviewed-by: dlong, mchung, dholmes

! src/hotspot/share/ci/ciMethod.cpp
! src/hotspot/share/ci/ciMethod.hpp
! src/hotspot/share/classfile/vmSymbols.hpp
! src/hotspot/share/oops/method.cpp
! src/hotspot/share/oops/method.hpp
! src/hotspot/share/opto/graphKit.cpp
+ test/jdk/java/lang/reflect/IllegalArgumentsTest.java

Changeset: e6b28e05
Author:    Jesper Wilhelmsson <jwilhelm at openjdk.org>
Date:      2021-12-16 00:26:36 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/e6b28e05c6f7698f230b04199932d4fc81f41a89

Merge


Changeset: 0dbe4c5d
Author:    Calvin Cheung <ccheung at openjdk.org>
Date:      2021-12-16 02:32:44 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/0dbe4c5d516a5e43934cb18f3becaf2a7f90999f

8278131: runtime/cds/appcds/dynamicArchive/* tests failing in loom repo

Reviewed-by: iklam, dholmes, minqi

! test/hotspot/jtreg/runtime/HiddenClasses/InstantiateHiddenClass.java
! test/hotspot/jtreg/runtime/cds/appcds/customLoader/test-classes/HelloUnload.java
! test/hotspot/jtreg/runtime/cds/appcds/customLoader/test-classes/OldClassApp.java
! test/hotspot/jtreg/runtime/cds/appcds/dynamicArchive/HelloDynamicCustom.java
! test/hotspot/jtreg/runtime/cds/appcds/dynamicArchive/LambdaCustomLoader.java
! test/hotspot/jtreg/runtime/cds/appcds/dynamicArchive/OldClassAndInf.java
! test/hotspot/jtreg/runtime/cds/appcds/dynamicArchive/PrintSharedArchiveAndExit.java
! test/hotspot/jtreg/runtime/cds/appcds/dynamicArchive/RegularHiddenClass.java
! test/hotspot/jtreg/runtime/cds/appcds/dynamicArchive/test-classes/CustomLoaderApp.java

Changeset: f6fbb5a8
Author:    Zhiqiang Zang <zhiqiang.zang at utexas.edu>
Committer: Jie Fu <jiefu at openjdk.org>
Date:      2021-12-16 03:57:29 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f6fbb5a80cfe630e76917397d21649709485d31d

8278471: Remove unreached rules in AddNode::IdealIL

Reviewed-by: jiefu, kvn

! src/hotspot/share/opto/addnode.cpp
! src/hotspot/share/opto/subnode.cpp
+ test/hotspot/jtreg/compiler/c2/irTests/TestSpecialCasesOf_AMinusB_Plus_CMinusD_InAddIdeal.java
! test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java

Changeset: 0bddd8af
Author:    Dmitry Batrak <dbatrak at openjdk.org>
Date:      2021-12-16 07:14:35 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/0bddd8af61b6c731f16b857c09de57ceefd72d06

8278050: Armenian text isn't rendered on macOS if text layout is performed

Reviewed-by: prr, serb

! src/java.desktop/macosx/classes/sun/font/CFont.java
! src/java.desktop/macosx/classes/sun/font/CFontManager.java

Changeset: d9b892c7
Author:    Fei Yang <felix.yang at huawei.com>
Date:      2021-12-16 03:25:57 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/d9b892c7aeced94f2007f1a5d9548588d043f63b

Merge branch 'master' into riscv-port

! src/hotspot/cpu/riscv/vm_version_riscv.cpp
! src/hotspot/cpu/riscv/vm_version_riscv.hpp
! src/hotspot/os/linux/os_linux.cpp
! src/hotspot/share/c1/c1_LIRAssembler.cpp
! src/hotspot/share/runtime/abstract_vm_version.cpp
! src/hotspot/share/runtime/arguments.cpp
+ src/hotspot/cpu/riscv/vm_version_riscv.cpp
+ src/hotspot/cpu/riscv/vm_version_riscv.hpp
! src/hotspot/os/linux/os_linux.cpp
! src/hotspot/share/c1/c1_LIRAssembler.cpp
! src/hotspot/share/runtime/abstract_vm_version.cpp
! src/hotspot/share/runtime/arguments.cpp


From yzhu at openjdk.java.net  Thu Dec 16 12:18:53 2021
From: yzhu at openjdk.java.net (Yanhong Zhu)
Date: Thu, 16 Dec 2021 12:18:53 GMT
Subject: [riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64
Message-ID: <Y6EZiKt8SenJDuq3UgJE6znPbq_gP3hHqph6IcBrtSA=.858673f2-21b3-4a75-a8a1-2f0345117649@github.com>

Rename Riscv64 to RISCV64 for consistence.

The related tests passed on QEMU:

- test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA1IntrinsicsOptionOnUnsupportedCPU.java
- test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA256IntrinsicsOptionOnUnsupportedCPU.java
- test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA512IntrinsicsOptionOnUnsupportedCPU.java
- test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHAOptionOnUnsupportedCPU.java
- test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java
- test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForUnsupportedRISCV64CPU.java
- test/hotspot/jtreg/runtime/NMT/CheckForProperDetailStackTrace.java
- test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java
- test/jdk/jdk/jfr/event/os/TestCPUInformation.java
- test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java
- test/lib/jdk/test/lib/Platform.java

-------------

Commit messages:
 - 8278895: riscv: Rename Riscv64 to RISCV64

Changes: https://git.openjdk.java.net/riscv-port/pull/33/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=33&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278895
  Stats: 32 lines in 16 files changed: 0 ins; 1 del; 31 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/33.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/33/head:pull/33

PR: https://git.openjdk.java.net/riscv-port/pull/33

From yzhu at openjdk.java.net  Thu Dec 16 12:53:45 2021
From: yzhu at openjdk.java.net (Yanhong Zhu)
Date: Thu, 16 Dec 2021 12:53:45 GMT
Subject: [riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64 [v2]
In-Reply-To: <Y6EZiKt8SenJDuq3UgJE6znPbq_gP3hHqph6IcBrtSA=.858673f2-21b3-4a75-a8a1-2f0345117649@github.com>
References: <Y6EZiKt8SenJDuq3UgJE6znPbq_gP3hHqph6IcBrtSA=.858673f2-21b3-4a75-a8a1-2f0345117649@github.com>
Message-ID: <VfLocHyk9hKxif7ZNkZHlCyWQCbHemmcK2P9wds7ZYs=.34dae7ca-77be-4df9-ae2c-8ba8b8f20534@github.com>

> Rename Riscv64 to RISCV64 for consistence.
> 
> The related tests passed on QEMU:
> 
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA1IntrinsicsOptionOnUnsupportedCPU.java
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA256IntrinsicsOptionOnUnsupportedCPU.java
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA512IntrinsicsOptionOnUnsupportedCPU.java
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHAOptionOnUnsupportedCPU.java
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForUnsupportedRISCV64CPU.java
> - test/hotspot/jtreg/runtime/NMT/CheckForProperDetailStackTrace.java
> - test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java
> - test/jdk/jdk/jfr/event/os/TestCPUInformation.java
> - test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java

Yanhong Zhu has updated the pull request incrementally with one additional commit since the last revision:

  modify RV64 to RISCV64

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/33/files
  - new: https://git.openjdk.java.net/riscv-port/pull/33/files/1958f7f6..06a56d51

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=33&range=01
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=33&range=00-01

  Stats: 1 line in 1 file changed: 0 ins; 0 del; 1 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/33.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/33/head:pull/33

PR: https://git.openjdk.java.net/riscv-port/pull/33

From yadongwang at openjdk.java.net  Fri Dec 17 03:40:48 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Fri, 17 Dec 2021 03:40:48 GMT
Subject: [riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64 [v2]
In-Reply-To: <VfLocHyk9hKxif7ZNkZHlCyWQCbHemmcK2P9wds7ZYs=.34dae7ca-77be-4df9-ae2c-8ba8b8f20534@github.com>
References: <Y6EZiKt8SenJDuq3UgJE6znPbq_gP3hHqph6IcBrtSA=.858673f2-21b3-4a75-a8a1-2f0345117649@github.com>
 <VfLocHyk9hKxif7ZNkZHlCyWQCbHemmcK2P9wds7ZYs=.34dae7ca-77be-4df9-ae2c-8ba8b8f20534@github.com>
Message-ID: <de7bhkIpAQ-pJL6nAh7_YhwBvV33jXQsWdjsESCqb8A=.beb784a8-3563-4ee9-8a02-2aaa276bbdcd@github.com>

On Thu, 16 Dec 2021 12:53:45 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

>> Rename Riscv64 to RISCV64 for consistence.
>> 
>> The related tests passed on QEMU:
>> 
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA1IntrinsicsOptionOnUnsupportedCPU.java
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA256IntrinsicsOptionOnUnsupportedCPU.java
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA512IntrinsicsOptionOnUnsupportedCPU.java
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHAOptionOnUnsupportedCPU.java
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForUnsupportedRISCV64CPU.java
>> - test/hotspot/jtreg/runtime/NMT/CheckForProperDetailStackTrace.java
>> - test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java
>> - test/jdk/jdk/jfr/event/os/TestCPUInformation.java
>> - test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java
>
> Yanhong Zhu has updated the pull request incrementally with one additional commit since the last revision:
> 
>   modify RV64 to RISCV64

src/hotspot/cpu/riscv/vm_version_riscv.cpp line 182:

> 180:   _no_of_sockets = _no_of_cores;
> 181:   snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "RISCV64");
> 182:   snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "RISCV64%s", _features_string);

Keep it here. It's supposed to be RV64.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/33

From duke at openjdk.java.net  Fri Dec 17 05:43:57 2021
From: duke at openjdk.java.net (guotaiping1)
Date: Fri, 17 Dec 2021 05:43:57 GMT
Subject: [riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64 [v2]
In-Reply-To: <de7bhkIpAQ-pJL6nAh7_YhwBvV33jXQsWdjsESCqb8A=.beb784a8-3563-4ee9-8a02-2aaa276bbdcd@github.com>
References: <Y6EZiKt8SenJDuq3UgJE6znPbq_gP3hHqph6IcBrtSA=.858673f2-21b3-4a75-a8a1-2f0345117649@github.com>
 <VfLocHyk9hKxif7ZNkZHlCyWQCbHemmcK2P9wds7ZYs=.34dae7ca-77be-4df9-ae2c-8ba8b8f20534@github.com>
 <de7bhkIpAQ-pJL6nAh7_YhwBvV33jXQsWdjsESCqb8A=.beb784a8-3563-4ee9-8a02-2aaa276bbdcd@github.com>
Message-ID: <sy9YajytmbVcSFpO6t76eKCM43M5uRJ_PFPVqOSRmg0=.d5e153ac-e4ff-4d5c-962e-7c511a34b439@github.com>

On Fri, 17 Dec 2021 03:37:34 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

>> Yanhong Zhu has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   modify RV64 to RISCV64
>
> src/hotspot/cpu/riscv/vm_version_riscv.cpp line 182:
> 
>> 180:   _no_of_sockets = _no_of_cores;
>> 181:   snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "RISCV64");
>> 182:   snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "RISCV64%s", _features_string);
> 
> Keep it here. It's supposed to be RV64.

'RV64' will cause the test/jdk/jdk/jfr/event/os/TestCPUInformation.java case fail.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/33

From yzhu at openjdk.java.net  Fri Dec 17 07:46:41 2021
From: yzhu at openjdk.java.net (Yanhong Zhu)
Date: Fri, 17 Dec 2021 07:46:41 GMT
Subject: [riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64 [v3]
In-Reply-To: <Y6EZiKt8SenJDuq3UgJE6znPbq_gP3hHqph6IcBrtSA=.858673f2-21b3-4a75-a8a1-2f0345117649@github.com>
References: <Y6EZiKt8SenJDuq3UgJE6znPbq_gP3hHqph6IcBrtSA=.858673f2-21b3-4a75-a8a1-2f0345117649@github.com>
Message-ID: <fyj9BJp-0aSk1kNs1lwIFYa_Algvyvvf-Lf7D4iryyw=.afa54e67-da3d-443b-b82c-4c182e06ad3d@github.com>

> Rename Riscv64 to RISCV64 for consistence.
> 
> The related tests passed on QEMU:
> 
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA1IntrinsicsOptionOnUnsupportedCPU.java
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA256IntrinsicsOptionOnUnsupportedCPU.java
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA512IntrinsicsOptionOnUnsupportedCPU.java
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHAOptionOnUnsupportedCPU.java
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForUnsupportedRISCV64CPU.java
> - test/hotspot/jtreg/runtime/NMT/CheckForProperDetailStackTrace.java
> - test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java
> - test/jdk/jdk/jfr/event/os/TestCPUInformation.java
> - test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java

Yanhong Zhu has updated the pull request incrementally with one additional commit since the last revision:

  add space

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/33/files
  - new: https://git.openjdk.java.net/riscv-port/pull/33/files/06a56d51..f512039a

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=33&range=02
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=33&range=01-02

  Stats: 1 line in 1 file changed: 0 ins; 0 del; 1 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/33.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/33/head:pull/33

PR: https://git.openjdk.java.net/riscv-port/pull/33

From yzhu at openjdk.java.net  Fri Dec 17 07:46:42 2021
From: yzhu at openjdk.java.net (Yanhong Zhu)
Date: Fri, 17 Dec 2021 07:46:42 GMT
Subject: [riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64 [v2]
In-Reply-To: <sy9YajytmbVcSFpO6t76eKCM43M5uRJ_PFPVqOSRmg0=.d5e153ac-e4ff-4d5c-962e-7c511a34b439@github.com>
References: <Y6EZiKt8SenJDuq3UgJE6znPbq_gP3hHqph6IcBrtSA=.858673f2-21b3-4a75-a8a1-2f0345117649@github.com>
 <VfLocHyk9hKxif7ZNkZHlCyWQCbHemmcK2P9wds7ZYs=.34dae7ca-77be-4df9-ae2c-8ba8b8f20534@github.com>
 <de7bhkIpAQ-pJL6nAh7_YhwBvV33jXQsWdjsESCqb8A=.beb784a8-3563-4ee9-8a02-2aaa276bbdcd@github.com>
 <sy9YajytmbVcSFpO6t76eKCM43M5uRJ_PFPVqOSRmg0=.d5e153ac-e4ff-4d5c-962e-7c511a34b439@github.com>
Message-ID: <oceBqamhA1CJxvb7WqnXbkNSwYZRVJ4ddCENYHfUpaA=.dc40704b-f795-413b-afcd-f842b19377d9@github.com>

On Fri, 17 Dec 2021 05:36:52 GMT, guotaiping1 <duke at openjdk.java.net> wrote:

>> src/hotspot/cpu/riscv/vm_version_riscv.cpp line 182:
>> 
>>> 180:   _no_of_sockets = _no_of_cores;
>>> 181:   snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "RISCV64");
>>> 182:   snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "RISCV64%s", _features_string);
>> 
>> Keep it here. It's supposed to be RV64.
>
> 'RV64' will cause the test/jdk/jdk/jfr/event/os/TestCPUInformation.java case fail.

Done.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/33

From duke at openjdk.java.net  Fri Dec 17 13:20:50 2021
From: duke at openjdk.java.net (guotaiping1)
Date: Fri, 17 Dec 2021 13:20:50 GMT
Subject: [riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64 [v3]
In-Reply-To: <fyj9BJp-0aSk1kNs1lwIFYa_Algvyvvf-Lf7D4iryyw=.afa54e67-da3d-443b-b82c-4c182e06ad3d@github.com>
References: <Y6EZiKt8SenJDuq3UgJE6znPbq_gP3hHqph6IcBrtSA=.858673f2-21b3-4a75-a8a1-2f0345117649@github.com>
 <fyj9BJp-0aSk1kNs1lwIFYa_Algvyvvf-Lf7D4iryyw=.afa54e67-da3d-443b-b82c-4c182e06ad3d@github.com>
Message-ID: <_BxCGKwVP5qgoCSZgocyoUmU-_3eOnbp2N9GoSblOuA=.d63cbaca-4f0b-458b-804b-889044540391@github.com>

On Fri, 17 Dec 2021 07:46:41 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

>> Rename Riscv64 to RISCV64 for consistence.
>> 
>> The related tests passed on QEMU:
>> 
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA1IntrinsicsOptionOnUnsupportedCPU.java
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA256IntrinsicsOptionOnUnsupportedCPU.java
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA512IntrinsicsOptionOnUnsupportedCPU.java
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHAOptionOnUnsupportedCPU.java
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForUnsupportedRISCV64CPU.java
>> - test/hotspot/jtreg/runtime/NMT/CheckForProperDetailStackTrace.java
>> - test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java
>> - test/jdk/jdk/jfr/event/os/TestCPUInformation.java
>> - test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java
>
> Yanhong Zhu has updated the pull request incrementally with one additional commit since the last revision:
> 
>   add space

Marked as reviewed by guotaiping1 at github.com (no known OpenJDK username).

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/33

From fyang at openjdk.java.net  Mon Dec 20 01:18:57 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Mon, 20 Dec 2021 01:18:57 GMT
Subject: [riscv-port] RFR: 8278895: riscv: Rename Riscv64 to RISCV64 [v3]
In-Reply-To: <fyj9BJp-0aSk1kNs1lwIFYa_Algvyvvf-Lf7D4iryyw=.afa54e67-da3d-443b-b82c-4c182e06ad3d@github.com>
References: <Y6EZiKt8SenJDuq3UgJE6znPbq_gP3hHqph6IcBrtSA=.858673f2-21b3-4a75-a8a1-2f0345117649@github.com>
 <fyj9BJp-0aSk1kNs1lwIFYa_Algvyvvf-Lf7D4iryyw=.afa54e67-da3d-443b-b82c-4c182e06ad3d@github.com>
Message-ID: <hfmRwt4KVpN6RIZDneQ21R7Rx4QoAQKWnKgoGFco6v0=.df06ceea-0061-4035-8fb8-6a41a4f840d3@github.com>

On Fri, 17 Dec 2021 07:46:41 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

>> Rename Riscv64 to RISCV64 for consistence.
>> 
>> The related tests passed on QEMU:
>> 
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA1IntrinsicsOptionOnUnsupportedCPU.java
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA256IntrinsicsOptionOnUnsupportedCPU.java
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA512IntrinsicsOptionOnUnsupportedCPU.java
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHAOptionOnUnsupportedCPU.java
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java
>> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForUnsupportedRISCV64CPU.java
>> - test/hotspot/jtreg/runtime/NMT/CheckForProperDetailStackTrace.java
>> - test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java
>> - test/jdk/jdk/jfr/event/os/TestCPUInformation.java
>> - test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java
>
> Yanhong Zhu has updated the pull request incrementally with one additional commit since the last revision:
> 
>   add space

Looks good. Thanks.

-------------

Marked as reviewed by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/33

From yzhu at openjdk.java.net  Mon Dec 20 01:24:00 2021
From: yzhu at openjdk.java.net (Yanhong Zhu)
Date: Mon, 20 Dec 2021 01:24:00 GMT
Subject: [riscv-port] Integrated: 8278895: riscv: Rename Riscv64 to RISCV64
In-Reply-To: <Y6EZiKt8SenJDuq3UgJE6znPbq_gP3hHqph6IcBrtSA=.858673f2-21b3-4a75-a8a1-2f0345117649@github.com>
References: <Y6EZiKt8SenJDuq3UgJE6znPbq_gP3hHqph6IcBrtSA=.858673f2-21b3-4a75-a8a1-2f0345117649@github.com>
Message-ID: <ekdNXeMti1IcfTQ63WoXmevTO8qSNxwO2HhAOPR3_Lc=.7a3b4cf2-1448-4ae8-ba6f-1cc90658c694@github.com>

On Thu, 16 Dec 2021 12:09:33 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

> Rename Riscv64 to RISCV64 for consistence.
> 
> The related tests passed on QEMU:
> 
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA1IntrinsicsOptionOnUnsupportedCPU.java
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA256IntrinsicsOptionOnUnsupportedCPU.java
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHA512IntrinsicsOptionOnUnsupportedCPU.java
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/TestUseSHAOptionOnUnsupportedCPU.java
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java
> - test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForUnsupportedRISCV64CPU.java
> - test/hotspot/jtreg/runtime/NMT/CheckForProperDetailStackTrace.java
> - test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java
> - test/jdk/jdk/jfr/event/os/TestCPUInformation.java
> - test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java

This pull request has now been integrated.

Changeset: 066d01ba
Author:    Yanhong Zhu <yzhu at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/066d01ba43f7d02ca99b70ab046efaa16e24f415
Stats:     33 lines in 17 files changed: 0 ins; 1 del; 32 mod

8278895: riscv: Rename Riscv64 to RISCV64

Co-authored-by: Taiping Guo <guotaiping1 at huawei.com>
Reviewed-by: fyang

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/33

From duke at openjdk.java.net  Mon Dec 20 02:13:13 2021
From: duke at openjdk.java.net (duke)
Date: Mon, 20 Dec 2021 02:13:13 GMT
Subject: git: openjdk/riscv-port: riscv-port: 31 new changesets
Message-ID: <e789a6df-5cbd-40df-84da-930fbc6129ec@openjdk.java.net>

Changeset: 7edcd348
Author:    Hamlin Li <mli at openjdk.org>
Date:      2021-12-16 11:35:42 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/7edcd348699b47050e4c5e3181c66fd0ee72830f

8278534: Remove some unnecessary code in MethodLiveness::init_basic_blocks

Reviewed-by: chagedorn

! src/hotspot/share/compiler/methodLiveness.cpp

Changeset: aae56398
Author:    Claes Redestad <redestad at openjdk.org>
Date:      2021-12-16 11:46:02 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/aae563981c89d922c51005626b39c31e377cadc5

8278642: Refactor java.util.Formatter

Reviewed-by: rriggs, naoto

! src/java.base/share/classes/java/util/Formatter.java

Changeset: e0700bf1
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-12-16 13:39:24 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/e0700bf1d464762d0ee52c08e7e8668e9c8cfc3f

8278763: Parallel: Remove grows_up/grows_down in PSVirtualSpace

Reviewed-by: tschatzl, mli

! src/hotspot/share/gc/parallel/psVirtualspace.cpp
! src/hotspot/share/gc/parallel/psVirtualspace.hpp

Changeset: 271d26f1
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-12-16 13:40:22 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/271d26f14149014d264e3a33cc0206f61856f7cd

8278601: Parallel: Remove redundant code in ObjectStartArray::initialize

Reviewed-by: sjohanss, mli

! src/hotspot/share/gc/parallel/objectStartArray.cpp

Changeset: f15a59ce
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-12-16 13:41:19 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f15a59ce72e7637620c2d3b5becf751809d13aed

8278756: Parallel: Drop PSOldGen::_reserved

Reviewed-by: tschatzl, mli

! src/hotspot/share/gc/parallel/objectStartArray.hpp
! src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp
! src/hotspot/share/gc/parallel/psOldGen.cpp
! src/hotspot/share/gc/parallel/psOldGen.hpp
! src/hotspot/share/gc/parallel/psParallelCompact.cpp
! src/hotspot/share/gc/parallel/psVirtualspace.cpp
! src/hotspot/share/gc/parallel/psVirtualspace.hpp
! src/hotspot/share/gc/parallel/psYoungGen.hpp
! src/hotspot/share/gc/parallel/vmStructs_parallelgc.hpp

Changeset: 937126b1
Author:    Zhengyu Gu <zgu at openjdk.org>
Date:      2021-12-16 15:23:02 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/937126b1406ff0f6ac0828310e5e09003692dcd3

8278551: Shenandoah: Adopt WorkerThread::worker_id() to replace Shenandoah specific implementation

Reviewed-by: rkennke

! src/hotspot/share/gc/shenandoah/shenandoahReferenceProcessor.cpp
! src/hotspot/share/gc/shenandoah/shenandoahThreadLocalData.hpp
! src/hotspot/share/gc/shenandoah/shenandoahUtils.cpp
! src/hotspot/share/gc/shenandoah/shenandoahUtils.hpp

Changeset: 20db7800
Author:    Sergey Tsypanov <sergei.tsypanov at yandex.ru>
Committer: Roger Riggs <rriggs at openjdk.org>
Date:      2021-12-16 21:39:08 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/20db7800a657b311eeac504a2bbae4adbc209dbf

8277868: Use Comparable.compare() instead of surrogate code

Reviewed-by: rriggs, aivanov

! src/java.base/share/classes/java/math/BigDecimal.java
! src/java.base/share/classes/java/net/CookieManager.java
! src/java.base/share/classes/java/util/Calendar.java
! src/java.base/share/classes/java/util/Date.java
! src/java.base/share/classes/java/util/UUID.java
! src/java.desktop/share/classes/java/awt/font/NumericShaper.java
! src/java.desktop/share/classes/java/awt/geom/Line2D.java
! src/java.desktop/share/classes/javax/swing/plaf/basic/BasicTableUI.java
! src/java.desktop/share/classes/javax/swing/text/GapContent.java
! src/java.desktop/share/classes/sun/awt/geom/Curve.java
! src/java.desktop/share/classes/sun/java2d/Spans.java
! src/java.desktop/share/classes/sun/java2d/loops/GraphicsPrimitiveMgr.java

Changeset: 8f5fdd86
Author:    Naoto Sato <naoto at openjdk.org>
Date:      2021-12-16 21:41:38 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8f5fdd864b6f1cf4a2d9d961d8d4118960f0751e

8278587: StringTokenizer(String, String, boolean) documentation bug

Reviewed-by: iris, joehw, lancea, rriggs, darcy

! src/java.base/share/classes/java/util/StringTokenizer.java

Changeset: 197c9f5a
Author:    David Holmes <dholmes at openjdk.org>
Date:      2021-12-16 22:17:53 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/197c9f5ac8cc0ebfcd9f33415b0dcd382cd8d15e

8268573: Remove expired flags in JDK 19

Reviewed-by: dcubed, pchilanomate, eosterlund

! src/hotspot/share/runtime/arguments.cpp
! src/java.base/share/man/java.1

Changeset: 7ce4aa89
Author:    Chris Plummer <cjplummer at openjdk.org>
Date:      2021-12-16 23:25:07 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/7ce4aa894279b76b6033bb4a1d0caa00d4213406

8276982: VM.class_hierarchy jcmd help output and man page text needs clarifications/improvements

Reviewed-by: stuefe, dholmes, sspitsyn

! src/hotspot/share/services/diagnosticCommand.cpp
! src/jdk.jcmd/share/man/jcmd.1

Changeset: e82310f3
Author:    Stuart Marks <smarks at openjdk.org>
Date:      2021-12-16 01:27:07 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/e82310f3605b37519129ea34b2a6f99ee3ccc63a

8278575: update jcmd GC.finalizer_info to list finalization status

Co-authored-by: David Holmes <dholmes at openjdk.org>
Reviewed-by: dholmes, kbarrett

! src/hotspot/share/services/diagnosticCommand.cpp

Changeset: aec1b039
Author:    Thomas Schatzl <tschatzl at openjdk.org>
Date:      2021-12-16 12:29:57 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/aec1b039b35b73db17c943cdd86949a92e64fcb6

8278389: SuspendibleThreadSet::_suspend_all should be volatile/atomic

Reviewed-by: ayang, mli

! src/hotspot/share/gc/shared/suspendibleThreadSet.cpp
! src/hotspot/share/gc/shared/suspendibleThreadSet.hpp

Changeset: be6b90d9
Author:    Stuart Marks <smarks at openjdk.org>
Date:      2021-12-16 17:35:32 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/be6b90d90b54883ff17f9f5ac0f271de37df7e2a

8278574: update --help-extra message to include default value of --finalization option

Reviewed-by: sundar, alanb, lancea, mchung

! src/java.base/share/classes/sun/launcher/resources/launcher.properties

Changeset: 634afe8c
Author:    Jesper Wilhelmsson <jwilhelm at openjdk.org>
Date:      2021-12-17 01:08:22 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/634afe8c5c0855eafb1639f54ecc8e9c9e568814

Merge

! src/hotspot/share/services/diagnosticCommand.cpp
! src/hotspot/share/services/diagnosticCommand.cpp

Changeset: 8c73ec15
Author:    Hamlin Li <mli at openjdk.org>
Date:      2021-12-17 03:29:28 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8c73ec155dd9324367d2a8e5f2e49da11683f8c8

8278891: G1: Call reset in G1RegionMarkStatsCache constructor

Reviewed-by: tschatzl, ayang

! src/hotspot/share/gc/g1/g1FullGCMarker.cpp
! src/hotspot/share/gc/g1/g1RegionMarkStatsCache.cpp

Changeset: 247ea71d
Author:    Dmitry Chuyko <dchuyko at openjdk.org>
Date:      2021-12-17 09:19:00 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/247ea71d24a251d29d9a5179e5b773df850e7261

8278826: Print error if Shenandoah flags are empty (instead of crashing)

Reviewed-by: rkennke, mli

! src/hotspot/share/gc/shenandoah/mode/shenandoahIUMode.cpp
! src/hotspot/share/gc/shenandoah/mode/shenandoahPassiveMode.cpp
! src/hotspot/share/gc/shenandoah/mode/shenandoahSATBMode.cpp
! src/hotspot/share/gc/shenandoah/shenandoahHeap.cpp

Changeset: 6412d57a
Author:    Weijun Wang <weijun at openjdk.org>
Date:      2021-12-17 12:14:17 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/6412d57a0a92ba08cc3db085b371ae1f7ba35ad5

8278560: X509KeyManagerImpl::getAliases might return a good key with others

Reviewed-by: xuelei

! src/java.base/share/classes/sun/security/ssl/X509KeyManagerImpl.java
+ test/jdk/sun/security/ssl/X509KeyManager/NoGoodKey.java

Changeset: abab1738
Author:    Roman Kennke <rkennke at openjdk.org>
Date:      2021-12-17 13:33:08 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/abab1738a702648e91f4c3ad91f71b7633914a31

8278568: Consolidate filler objects

Reviewed-by: tschatzl, mli, ayang

! src/hotspot/share/gc/parallel/psPromotionLAB.cpp
! src/hotspot/share/gc/parallel/psPromotionLAB.hpp
! src/hotspot/share/gc/shared/collectedHeap.cpp
! src/hotspot/share/gc/shared/collectedHeap.hpp
! src/hotspot/share/gc/shared/space.cpp
! src/hotspot/share/gc/shared/space.hpp
! src/hotspot/share/oops/oop.hpp

Changeset: 3607a5cd
Author:    Coleen Phillimore <coleenp at openjdk.org>
Date:      2021-12-17 13:42:54 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3607a5cdd9a3013851c8faefd346f04934f897e6

8277216: Examine InstanceKlass::_misc_flags for concurrency issues

Reviewed-by: hseigel, dholmes

! src/hotspot/share/oops/instanceKlass.hpp
! src/hotspot/share/utilities/accessFlags.hpp

Changeset: a68f28ce
Author:    Nils Eliasson <neliasso at openjdk.org>
Date:      2021-12-17 15:08:45 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/a68f28cea6a726aa57c04a4fc5a665cae3513154

8278909: Unproblemlist AdaptiveBlocking001

Reviewed-by: chagedorn, eosterlund, stefank

! test/hotspot/jtreg/ProblemList-zgc.txt

Changeset: e45e0b05
Author:    Phil Race <prr at openjdk.org>
Date:      2021-12-17 15:10:03 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/e45e0b05b9e8da8da72bf227cede319fa207a551

8278937: JCK test for java_awt/geom/Line2D.Float fails after 8277868

Reviewed-by: jdv, kcr, rriggs

! src/java.desktop/share/classes/java/awt/geom/Line2D.java
! src/java.desktop/share/classes/sun/awt/geom/Curve.java
! src/java.desktop/share/classes/sun/java2d/Spans.java

Changeset: 769f14db
Author:    Harold Seigel <hseigel at openjdk.org>
Date:      2021-12-17 15:11:16 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/769f14db847813f5a3601e9ec21e6cadbd99ee96

8278384: Bytecodes::result_type() for arraylength returns T_VOID instead of T_INT

Reviewed-by: lfoltan, dholmes

! src/hotspot/share/interpreter/bytecodeUtils.cpp
! src/hotspot/share/interpreter/bytecodes.cpp

Changeset: b17f8d5b
Author:    Gilles Duboscq <gdub at openjdk.org>
Date:      2021-12-17 15:36:07 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/b17f8d5b6c4d4ec75bb57f1d2009e30332bdb3ce

8278954: Using clang together with devkit on linux doesn't work for building

Reviewed-by: erikj

! make/autoconf/flags.m4

Changeset: 0bfc204a
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-12-17 15:45:16 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/0bfc204a78878872f16019bc75dac7844876ed60

8278956: Remove unimplemented PLAB::allocate_aligned

Reviewed-by: tschatzl

! src/hotspot/share/gc/shared/plab.hpp

Changeset: 022e4f0f
Author:    Andrey Turbanov <turbanoff at gmail.com>
Committer: Vicente Romero <vromero at openjdk.org>
Date:      2021-12-17 18:52:37 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/022e4f0f1c4862315b34595d6df228a49f67cb2e

8275242: Remove redundant stream() call before forEach in jdk.compiler

Reviewed-by: vromero

! src/jdk.compiler/share/classes/com/sun/tools/javac/api/JavacTrees.java
! src/jdk.compiler/share/classes/com/sun/tools/javac/code/TypeAnnotations.java
! src/jdk.compiler/share/classes/com/sun/tools/javac/comp/AttrRecover.java
! src/jdk.compiler/share/classes/com/sun/tools/javac/comp/InferenceContext.java
! src/jdk.compiler/share/classes/com/sun/tools/javac/processing/JavacProcessingEnvironment.java

Changeset: 905b7639
Author:    liach <liach at users.noreply.github.com>
Committer: Mandy Chung <mchung at openjdk.org>
Date:      2021-12-17 22:23:33 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/905b7639424a0fa80f81f734f6fdae1b5018a14a

8261404: Class.getReflectionFactory() is not thread-safe

Reviewed-by: rriggs, mchung

! src/java.base/share/classes/java/lang/Class.java

Changeset: cc44e137
Author:    merykitty <anhmdq99 at gmail.com>
Committer: Vladimir Kozlov <kvn at openjdk.org>
Date:      2021-12-17 23:42:28 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/cc44e137973808436311aaaa50916d051759f705

8278623: compiler/vectorapi/reshape/TestVectorCastAVX512.java after JDK-8259610

Reviewed-by: kvn, chagedorn, psandoz

! test/hotspot/jtreg/ProblemList.txt
+ test/hotspot/jtreg/compiler/vectorapi/reshape/TestVectorCastAVX512BW.java
! test/hotspot/jtreg/compiler/vectorapi/reshape/TestVectorReinterpret.java
! test/hotspot/jtreg/compiler/vectorapi/reshape/tests/TestVectorCast.java
! test/hotspot/jtreg/compiler/vectorapi/reshape/tests/TestVectorDoubleExpandShrink.java
! test/hotspot/jtreg/compiler/vectorapi/reshape/tests/TestVectorExpandShrink.java
! test/hotspot/jtreg/compiler/vectorapi/reshape/tests/TestVectorRebracket.java
! test/hotspot/jtreg/compiler/vectorapi/reshape/utils/TestCastMethods.java
! test/hotspot/jtreg/compiler/vectorapi/reshape/utils/UnsafeUtils.java
! test/hotspot/jtreg/compiler/vectorapi/reshape/utils/VectorReshapeHelper.java

Changeset: 3c10b5db
Author:    Guoxiong Li <gli at openjdk.org>
Date:      2021-12-18 04:16:44 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3c10b5db38455b8aed88599f5743fd846bd0913e

8278104: C1 should support the compiler directive 'BreakAtExecute'

Reviewed-by: xliu, phh, kvn

! src/hotspot/cpu/aarch64/c1_MacroAssembler_aarch64.cpp
! src/hotspot/cpu/arm/c1_MacroAssembler_arm.cpp
! src/hotspot/cpu/ppc/c1_MacroAssembler_ppc.cpp
! src/hotspot/cpu/s390/c1_MacroAssembler_s390.cpp
! src/hotspot/cpu/x86/c1_MacroAssembler_x86.cpp
! src/hotspot/share/c1/c1_LIRAssembler.cpp
! src/hotspot/share/c1/c1_MacroAssembler.hpp
! src/hotspot/share/compiler/compilerDirectives.cpp

Changeset: 6f0e8da6
Author:    Doug Simon <dnsimon at openjdk.org>
Date:      2021-12-18 06:48:00 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/6f0e8da6d3bef340299e48977d5e17d05eabe682

8278871: [JVMCI] assert((uint)reason < 2* _trap_hist_limit) failed: oob

Reviewed-by: kvn, never, dlong

! src/hotspot/share/jvmci/vmStructs_jvmci.cpp
! src/hotspot/share/oops/methodData.hpp
! src/hotspot/share/runtime/deoptimization.cpp
! src/hotspot/share/runtime/deoptimization.hpp
! src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot/src/jdk/vm/ci/hotspot/HotSpotVMConfig.java

Changeset: 63e43030
Author:    Alex Menkov <amenkov at openjdk.org>
Date:      2021-12-18 08:08:47 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/63e43030ed1260d14df950342c39a377231a3f40

8278519: serviceability/jvmti/FieldAccessWatch/FieldAccessWatch.java failed "assert(handle != __null) failed: JNI handle should not be null"

Reviewed-by: cjplummer, sspitsyn

! test/hotspot/jtreg/serviceability/jvmti/FieldAccessWatch/FieldAccessWatch.java
! test/hotspot/jtreg/serviceability/jvmti/FieldAccessWatch/libFieldAccessWatch.c

Changeset: a7e7183a
Author:    Fei Yang <felix.yang at huawei.com>
Date:      2021-12-19 21:09:31 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/a7e7183a46a7e4a7cd2585b88f505e9f88113c02

Merge branch 'master' into riscv-port

! src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp
! src/hotspot/share/c1/c1_LIRAssembler.cpp
! src/hotspot/share/runtime/arguments.cpp
+ src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp
! src/hotspot/share/c1/c1_LIRAssembler.cpp
! src/hotspot/share/runtime/arguments.cpp


From xlinzheng at openjdk.java.net  Mon Dec 20 08:16:28 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Mon, 20 Dec 2021 08:16:28 GMT
Subject: [riscv-port] RFR: 8278994: riscv: RVC: basic instruction set
Message-ID: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>

Hi team,

This patch includes the basic definition of the RVC instruction set and some cleanups. Tested a simple `test/hotspot/jtreg/compiler/` folder on qemu.

Thanks,
Xiaolin

-------------

Commit messages:
 - RVC: basic instruction set

Changes: https://git.openjdk.java.net/riscv-port/pull/34/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=34&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278994
  Stats: 627 lines in 8 files changed: 607 ins; 3 del; 17 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/34.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/34/head:pull/34

PR: https://git.openjdk.java.net/riscv-port/pull/34

From felix.yang at huawei.com  Mon Dec 20 09:12:30 2021
From: felix.yang at huawei.com (Yangfei (Felix))
Date: Mon, 20 Dec 2021 09:12:30 +0000
Subject: CFV: New RISC-V Port Committer: Yanhong Zhu
Message-ID: <f81314033eaa4affa992a7c9114f1440@huawei.com>

I hereby nominate Yanhong Zhu (yzhu) to RISC-V Port Committer.

Yanhong Zhu has been engaged in the development of the OpenJDK riscv-port since 2020.
She has contributed 8 sponsored patches to JDK and RISC-V Port project.

Votes are due by 9:00 UTC on Monday 3, January 2022.

Only current RISC-V Port Committers [1] are eligible to vote on this nomination.
Votes must be cast in the open by replying to this mailing list.

For Lazy Consensus voting instructions, see [2].

Thanks,
Felix

[1] https://openjdk.java.net/census
[2] https://openjdk.java.net/projects/#committer-vote

=========

8255287: aarch64: fix SVE patterns for vector shift count
8276792: RISC-V Port: Initial support for RV64GV
8277167: riscv: Remove unnecessary register declaration for lr
8277036: riscv: Get CPU features from the auxiliary vector on Linux
8277440: riscv: Move UseVExt from product to experimental
8276832: riscv: typo in LIR_Assembler::check_no_conflict
8278547: riscv: Refactor moving assembler functions for vector instructions into separate file
8278895: riscv: Rename Riscv64 to RISCV64

From felix.yang at huawei.com  Mon Dec 20 09:13:18 2021
From: felix.yang at huawei.com (Yangfei (Felix))
Date: Mon, 20 Dec 2021 09:13:18 +0000
Subject: CFV: New RISC-V Port Committer: Yanhong Zhu
Message-ID: <f21349c3997a46028412118c54d342ea@huawei.com>

Vote: yes

> -----Original Message-----
> From: Yangfei (Felix)
> Sent: Monday, December 20, 2021 5:12 PM
> To: 'riscv-port-dev at openjdk.java.net' <riscv-port-dev at openjdk.java.net>
> Subject: CFV: New RISC-V Port Committer: Yanhong Zhu
> 
> I hereby nominate Yanhong Zhu (yzhu) to RISC-V Port Committer.
> 
> Yanhong Zhu has been engaged in the development of the OpenJDK riscv-
> port since 2020.
> She has contributed 8 sponsored patches to JDK and RISC-V Port project.
> 
> Votes are due by 9:00 UTC on Monday 3, January 2022.
> 
> Only current RISC-V Port Committers [1] are eligible to vote on this
> nomination.
> Votes must be cast in the open by replying to this mailing list.
> 
> For Lazy Consensus voting instructions, see [2].
> 
> Thanks,
> Felix
> 
> [1] https://openjdk.java.net/census
> [2] https://openjdk.java.net/projects/#committer-vote
> 
> =========
> 
> 8255287: aarch64: fix SVE patterns for vector shift count
> 8276792: RISC-V Port: Initial support for RV64GV
> 8277167: riscv: Remove unnecessary register declaration for lr
> 8277036: riscv: Get CPU features from the auxiliary vector on Linux
> 8277440: riscv: Move UseVExt from product to experimental
> 8276832: riscv: typo in LIR_Assembler::check_no_conflict
> 8278547: riscv: Refactor moving assembler functions for vector instructions
> into separate file
> 8278895: riscv: Rename Riscv64 to RISCV64

From yadongwang at openjdk.java.net  Mon Dec 20 09:37:17 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Mon, 20 Dec 2021 09:37:17 GMT
Subject: [riscv-port] RFR: 8278890: riscv: Missing features string in
 VM_Version
Message-ID: <mhTZtlAFryRijkKZKLLzyYXh7ia2Rsn__ho9bs-DXYs=.2759bb34-1f56-4e5f-88bc-6e52d21000ed@github.com>

The features_string of VM_Version is supposed to be "sifive,u74-mc,rv64imafdc" for the unmatched board, which is made up of "uarch" and "isa" in /proc/cpuinfo.
In contrast, it's "family 6 model 79 stepping 1 microcode 0xb000036, cx8, cmov, fxsr, ht, mmx, 3dnowpref, sse, sse2, sse3, ssse3, sse4.1, sse4.2, popcnt, lzcnt, tsc, tscinvbit, avx, avx2, aes, erms, clmul, bmi1, bmi2, rtm, adx, fma, vzeroupper, clflush" in a x86 platform, and "0x41:0x0:0xd08:2, fp, simd, evtstrm, aes, pmull, sha1, sha256, crc" in aarch64.
After this PR, the following output is displayed when you run this test case `test/jdk/jdk/jfr/event/os/TestCPUInformation.java` on some common riscv platforms:
1. unmatched:

Event: jdk.CPUInformation {
  startTime = 15:54:00.844 (2021-12-20)
  cpu = "RISCV64"
  description = "RISCV64 sifive,u74-mc,rv64imafdc"
  sockets = 4
  cores = 4
  hwThreads = 4
}

2. D1:

Event: jdk.CPUInformation {
  startTime = 17:04:39.520 (2021-12-20)
  cpu = "RISCV64"
  description = "RISCV64 rv64imafdcv"
  sockets = 1
  cores = 1
  hwThreads = 1
}

-------------

Commit messages:
 - 8278890: riscv: Missing features string in VM_Version

Changes: https://git.openjdk.java.net/riscv-port/pull/35/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=35&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278890
  Stats: 49 lines in 3 files changed: 29 ins; 6 del; 14 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/35.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/35/head:pull/35

PR: https://git.openjdk.java.net/riscv-port/pull/35

From shade at redhat.com  Mon Dec 20 11:01:30 2021
From: shade at redhat.com (Aleksey Shipilev)
Date: Mon, 20 Dec 2021 12:01:30 +0100
Subject: CFV: New RISC-V Port Committer: Yanhong Zhu
In-Reply-To: <f81314033eaa4affa992a7c9114f1440@huawei.com>
References: <f81314033eaa4affa992a7c9114f1440@huawei.com>
Message-ID: <80c8c068-6f31-d29c-4956-f673f866edee@redhat.com>

Vote: yes

On 12/20/21 10:12 AM, Yangfei (Felix) wrote:
> I hereby nominate Yanhong Zhu (yzhu) to RISC-V Port Committer.

-- 
Thanks,
-Aleksey


From fjiang at openjdk.java.net  Tue Dec 21 01:27:05 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Tue, 21 Dec 2021 01:27:05 GMT
Subject: [riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd
Message-ID: <TakqWYumLto3fsFenakfk5QRKi7-0sVfIazl3Wjka7Y=.5cf6ee76-8924-4f89-85ef-49bc53268f8e@github.com>

BigInteger intrinsic: mulAdd intrinsic is missed in current vm. It should be implemented.
The JMH test of mulAdd intrinsic on the matched board shows that the performance can be improved by 0.69%~21.91% when the length of BigInteger changed from 1 to 5000, compared with that of C2.
| length | intrinsic(ops/ms) | no intrinsic(ops/ms) | intrinsic / no intrinsic |
| ------ | ------ | ------ | ------ | 
| 1 | 1643.111 | 1623.814 | 1.18% |
| 2 | 1597.927 | 1585.216 | 0.80% |
| 3 | 1542.249 | 1502.455 | 2.65% |
| 5 | 1533.371 | 1522.837 | 0.69% |
| 10 | 1377.683 | 1361.718 | 1.17% |
| 50 | 925.826 | 844.276 | 9.62% |
| 100 | 638.767 | 576.276 | 10.84% |
| 1000 | 99.870 | 84.796 | 17.78% |
| 2000 | 51.511 | 43.624 | 18.08% |
| 5000 | 18.017 | 14.779 | 21.91% |

-------------

Commit messages:
 - 8278644: riscv: Intrinsify mulAdd

Changes: https://git.openjdk.java.net/riscv-port/pull/36/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=36&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278644
  Stats: 106 lines in 4 files changed: 106 ins; 0 del; 0 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/36.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/36/head:pull/36

PR: https://git.openjdk.java.net/riscv-port/pull/36

From fyang at openjdk.java.net  Tue Dec 21 01:37:42 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Tue, 21 Dec 2021 01:37:42 GMT
Subject: [riscv-port] RFR: 8278890: riscv: Missing features string in
 VM_Version
In-Reply-To: <mhTZtlAFryRijkKZKLLzyYXh7ia2Rsn__ho9bs-DXYs=.2759bb34-1f56-4e5f-88bc-6e52d21000ed@github.com>
References: <mhTZtlAFryRijkKZKLLzyYXh7ia2Rsn__ho9bs-DXYs=.2759bb34-1f56-4e5f-88bc-6e52d21000ed@github.com>
Message-ID: <P05sMr_oYT6bbatxDkjxn_2Vg4gIaf-NWp5oE4EtlSY=.7e334c41-2f7f-45f1-8387-2f66db69b1f2@github.com>

On Mon, 20 Dec 2021 09:30:58 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> The features_string of VM_Version is supposed to be "sifive,u74-mc,rv64imafdc" for the unmatched board, which is made up of "uarch" and "isa" in /proc/cpuinfo.
> In contrast, it's "family 6 model 79 stepping 1 microcode 0xb000036, cx8, cmov, fxsr, ht, mmx, 3dnowpref, sse, sse2, sse3, ssse3, sse4.1, sse4.2, popcnt, lzcnt, tsc, tscinvbit, avx, avx2, aes, erms, clmul, bmi1, bmi2, rtm, adx, fma, vzeroupper, clflush" in a x86 platform, and "0x41:0x0:0xd08:2, fp, simd, evtstrm, aes, pmull, sha1, sha256, crc" in aarch64.
> After this PR, the following output is displayed when you run this test case `test/jdk/jdk/jfr/event/os/TestCPUInformation.java` on some common riscv platforms:
> 1. unmatched:
> 
> Event: jdk.CPUInformation {
>   startTime = 15:54:00.844 (2021-12-20)
>   cpu = "RISCV64"
>   description = "RISCV64 sifive,u74-mc,rv64imafdc"
>   sockets = 4
>   cores = 4
>   hwThreads = 4
> }
> 
> 2. D1:
> 
> Event: jdk.CPUInformation {
>   startTime = 17:04:39.520 (2021-12-20)
>   cpu = "RISCV64"
>   description = "RISCV64 rv64imafdcv"
>   sockets = 1
>   cores = 1
>   hwThreads = 1
> }

Looks good.

-------------

Marked as reviewed by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/35

From fyang at openjdk.java.net  Tue Dec 21 01:40:45 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Tue, 21 Dec 2021 01:40:45 GMT
Subject: [riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd
In-Reply-To: <TakqWYumLto3fsFenakfk5QRKi7-0sVfIazl3Wjka7Y=.5cf6ee76-8924-4f89-85ef-49bc53268f8e@github.com>
References: <TakqWYumLto3fsFenakfk5QRKi7-0sVfIazl3Wjka7Y=.5cf6ee76-8924-4f89-85ef-49bc53268f8e@github.com>
Message-ID: <NNyhftZ0H99yIAJEqk62QdQI1Me0ZtDwlW2jwZxO3Io=.96359647-294c-48fb-8ed7-028c7665f5eb@github.com>

On Tue, 21 Dec 2021 01:15:43 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> BigInteger intrinsic: mulAdd intrinsic is missed in current vm. It should be implemented.
> The JMH test of mulAdd intrinsic on the matched board shows that the performance can be improved by 0.69%~21.91% when the length of BigInteger changed from 1 to 5000, compared with that of C2.
> | length | intrinsic(ops/ms) | no intrinsic(ops/ms) | intrinsic / no intrinsic |
> | ------ | ------ | ------ | ------ | 
> | 1 | 1643.111 | 1623.814 | 1.18% |
> | 2 | 1597.927 | 1585.216 | 0.80% |
> | 3 | 1542.249 | 1502.455 | 2.65% |
> | 5 | 1533.371 | 1522.837 | 0.69% |
> | 10 | 1377.683 | 1361.718 | 1.17% |
> | 50 | 925.826 | 844.276 | 9.62% |
> | 100 | 638.767 | 576.276 | 10.84% |
> | 1000 | 99.870 | 84.796 | 17.78% |
> | 2000 | 51.511 | 43.624 | 18.08% |
> | 5000 | 18.017 | 14.779 | 21.91% |

Could you please post a link to the jmh test used here? Thanks.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/36

From fyang at openjdk.java.net  Tue Dec 21 01:48:43 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Tue, 21 Dec 2021 01:48:43 GMT
Subject: [riscv-port] RFR: 8278994: riscv: RVC: basic instruction set
In-Reply-To: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
References: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
Message-ID: <Un2f4Xkue4ys4WaGEqeR9R2je64I2wRjzVaSHqshTQI=.4639c89f-344c-4556-930b-41299bce3ce6@github.com>

On Mon, 20 Dec 2021 08:10:10 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
> 
> This patch includes the basic definition of the RVC instruction set and some cleanups. Tested a simple `test/hotspot/jtreg/compiler/` folder on qemu.
> 
> Thanks,
> Xiaolin

Looks like the previous discussion about compressible region is not reflected here in this PR. Could you please explain your approach?

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/34

From yadongwang at openjdk.java.net  Tue Dec 21 03:33:41 2021
From: yadongwang at openjdk.java.net (Yadong Wang)
Date: Tue, 21 Dec 2021 03:33:41 GMT
Subject: [riscv-port] Integrated: 8278890: riscv: Missing features string in
 VM_Version
In-Reply-To: <mhTZtlAFryRijkKZKLLzyYXh7ia2Rsn__ho9bs-DXYs=.2759bb34-1f56-4e5f-88bc-6e52d21000ed@github.com>
References: <mhTZtlAFryRijkKZKLLzyYXh7ia2Rsn__ho9bs-DXYs=.2759bb34-1f56-4e5f-88bc-6e52d21000ed@github.com>
Message-ID: <qM5vInsukP_hfd3VjiR9BJaTJIYiLyDiinlv4nbQkpc=.efa4c4a7-c4b9-4961-8531-654d4a5fdd22@github.com>

On Mon, 20 Dec 2021 09:30:58 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> The features_string of VM_Version is supposed to be "sifive,u74-mc,rv64imafdc" for the unmatched board, which is made up of "uarch" and "isa" in /proc/cpuinfo.
> In contrast, it's "family 6 model 79 stepping 1 microcode 0xb000036, cx8, cmov, fxsr, ht, mmx, 3dnowpref, sse, sse2, sse3, ssse3, sse4.1, sse4.2, popcnt, lzcnt, tsc, tscinvbit, avx, avx2, aes, erms, clmul, bmi1, bmi2, rtm, adx, fma, vzeroupper, clflush" in a x86 platform, and "0x41:0x0:0xd08:2, fp, simd, evtstrm, aes, pmull, sha1, sha256, crc" in aarch64.
> After this PR, the following output is displayed when you run this test case `test/jdk/jdk/jfr/event/os/TestCPUInformation.java` on some common riscv platforms:
> 1. unmatched:
> 
> Event: jdk.CPUInformation {
>   startTime = 15:54:00.844 (2021-12-20)
>   cpu = "RISCV64"
>   description = "RISCV64 sifive,u74-mc,rv64imafdc"
>   sockets = 4
>   cores = 4
>   hwThreads = 4
> }
> 
> 2. D1:
> 
> Event: jdk.CPUInformation {
>   startTime = 17:04:39.520 (2021-12-20)
>   cpu = "RISCV64"
>   description = "RISCV64 rv64imafdcv"
>   sockets = 1
>   cores = 1
>   hwThreads = 1
> }
> 
> 
> Hotspot and jdk tier1 passed on the unmatched, and all jtreg tests were tested on Qemu without new failures.

This pull request has now been integrated.

Changeset: 9086f8c9
Author:    Yadong Wang <yadongwang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/9086f8c91c9b6508975c655fa61cedec642e6842
Stats:     49 lines in 3 files changed: 29 ins; 6 del; 14 mod

8278890: riscv: Missing features string in VM_Version

Reviewed-by: fyang

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/35

From xlinzheng at openjdk.java.net  Tue Dec 21 05:55:32 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Tue, 21 Dec 2021 05:55:32 GMT
Subject: [riscv-port] RFR: 8278994: riscv: RVC: basic instruction set
In-Reply-To: <Un2f4Xkue4ys4WaGEqeR9R2je64I2wRjzVaSHqshTQI=.4639c89f-344c-4556-930b-41299bce3ce6@github.com>
References: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
 <Un2f4Xkue4ys4WaGEqeR9R2je64I2wRjzVaSHqshTQI=.4639c89f-344c-4556-930b-41299bce3ce6@github.com>
Message-ID: <S_AGDXJI0H2E3kA5HhFZMN9rw_7opbHBR6V7bkV6vRU=.12cd8e66-0e1b-448c-b8e1-b882e0ec2254@github.com>

On Tue, 21 Dec 2021 01:45:25 GMT, Fei Yang <fyang at openjdk.org> wrote:

> Looks like the previous discussion about compressible region is not reflected here in this PR. Could you please explain your approach?

Thanks for the reviews, Felix. The Region things are at [here](https://github.com/openjdk/riscv-port/pull/34/files#diff-d09fa54666353b5d9df5bbaa019c8e8351f6bca1091795dfb14615cdfb792b13R55-R60) and [here](https://github.com/openjdk/riscv-port/pull/34/files#diff-d09fa54666353b5d9df5bbaa019c8e8351f6bca1091795dfb14615cdfb792b13R560-R579), and currently, there is no usage of them. Besides, I sent messages to Yadong privately to discuss the previous design `RVC_Assembler` things. Maybe this patch could hold for a little moment after the discussion.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/34

From fjiang at openjdk.java.net  Tue Dec 21 07:50:39 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Tue, 21 Dec 2021 07:50:39 GMT
Subject: [riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd
In-Reply-To: <NNyhftZ0H99yIAJEqk62QdQI1Me0ZtDwlW2jwZxO3Io=.96359647-294c-48fb-8ed7-028c7665f5eb@github.com>
References: <TakqWYumLto3fsFenakfk5QRKi7-0sVfIazl3Wjka7Y=.5cf6ee76-8924-4f89-85ef-49bc53268f8e@github.com>
 <NNyhftZ0H99yIAJEqk62QdQI1Me0ZtDwlW2jwZxO3Io=.96359647-294c-48fb-8ed7-028c7665f5eb@github.com>
Message-ID: <_YjY5ZXiPxC93YKFvV6rRk4YEV_z24NsFJTo5VQ87LE=.313d76f0-d002-4005-86ed-974e5cac8f46@github.com>

On Tue, 21 Dec 2021 01:37:24 GMT, Fei Yang <fyang at openjdk.org> wrote:

> Could you please post a link to the jmh test used here? Thanks.

Thanks for your reminder, it has been added.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/36

From fyang at openjdk.java.net  Tue Dec 21 08:44:33 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Tue, 21 Dec 2021 08:44:33 GMT
Subject: [riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd
In-Reply-To: <TakqWYumLto3fsFenakfk5QRKi7-0sVfIazl3Wjka7Y=.5cf6ee76-8924-4f89-85ef-49bc53268f8e@github.com>
References: <TakqWYumLto3fsFenakfk5QRKi7-0sVfIazl3Wjka7Y=.5cf6ee76-8924-4f89-85ef-49bc53268f8e@github.com>
Message-ID: <5DndLzTjseGU3H1rJtv3ypkvkQUSNZkiaIvhSgcMkd4=.280cc590-7766-4faf-8b0b-514212a3d4ee@github.com>

On Tue, 21 Dec 2021 01:15:43 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> BigInteger intrinsic: mulAdd intrinsic is missed in current vm. It should be implemented.
> The JMH test of mulAdd intrinsic on the matched board shows that the performance can be improved by 0.69%~21.91% when the length of BigInteger changed from 1 to 5000, compared with that of C2.
> JMH test: [MyBenchmark.java](https://bugs.openjdk.java.net/secure/attachment/97414/MyBenchmark.java)
> 
> Performed full jtreg test with qemu without new failures.
> 
> Results list as follows
> | length | intrinsic(ops/ms) | no intrinsic(ops/ms) | intrinsic / no intrinsic |
> | ------ | ------ | ------ | ------ | 
> | 1 | 1643.111 | 1623.814 | 1.18% |
> | 2 | 1597.927 | 1585.216 | 0.80% |
> | 3 | 1542.249 | 1502.455 | 2.65% |
> | 5 | 1533.371 | 1522.837 | 0.69% |
> | 10 | 1377.683 | 1361.718 | 1.17% |
> | 50 | 925.826 | 844.276 | 9.62% |
> | 100 | 638.767 | 576.276 | 10.84% |
> | 1000 | 99.870 | 84.796 | 17.78% |
> | 2000 | 51.511 | 43.624 | 18.08% |
> | 5000 | 18.017 | 14.779 | 21.91% |

Changes requested by fyang (Lead).

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3049:

> 3047:                              Register len, Register k, Register tmp) {
> 3048:   Label L_tail_loop, L_unroll, L_end;
> 3049:   mv(tmp, out);

I think this "mv" instruction could be moved after the zero check for"len". Then we will save one instruction when "len" is zero.

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3062:

> 3060:   blt(len, tmp, L_tail_loop);
> 3061:   bind(L_unroll);
> 3062:   for (unsigned i = 0; i < unroll; i++) {

Better to change type of "i" into signed, i.e., "for (int i = 0; i < unroll; i++)"

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/36

From fjiang at openjdk.java.net  Tue Dec 21 09:06:25 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Tue, 21 Dec 2021 09:06:25 GMT
Subject: [riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd [v2]
In-Reply-To: <TakqWYumLto3fsFenakfk5QRKi7-0sVfIazl3Wjka7Y=.5cf6ee76-8924-4f89-85ef-49bc53268f8e@github.com>
References: <TakqWYumLto3fsFenakfk5QRKi7-0sVfIazl3Wjka7Y=.5cf6ee76-8924-4f89-85ef-49bc53268f8e@github.com>
Message-ID: <jtLCTBpSoVPXQZk4ZsyvS_OHFf7iJfrhceDoMNyFk1A=.610a5fa8-0945-421b-84de-490e847ba5d7@github.com>

> BigInteger intrinsic: mulAdd intrinsic is missed in current vm. It should be implemented.
> The JMH test of mulAdd intrinsic on the matched board shows that the performance can be improved by 0.69%~21.91% when the length of BigInteger changed from 1 to 5000, compared with that of C2.
> JMH test: [MyBenchmark.java](https://bugs.openjdk.java.net/secure/attachment/97414/MyBenchmark.java)
> 
> Performed full jtreg test with qemu without new failures.
> 
> Results list as follows
> | length | intrinsic(ops/ms) | no intrinsic(ops/ms) | intrinsic / no intrinsic |
> | ------ | ------ | ------ | ------ | 
> | 1 | 1643.111 | 1623.814 | 1.18% |
> | 2 | 1597.927 | 1585.216 | 0.80% |
> | 3 | 1542.249 | 1502.455 | 2.65% |
> | 5 | 1533.371 | 1522.837 | 0.69% |
> | 10 | 1377.683 | 1361.718 | 1.17% |
> | 50 | 925.826 | 844.276 | 9.62% |
> | 100 | 638.767 | 576.276 | 10.84% |
> | 1000 | 99.870 | 84.796 | 17.78% |
> | 2000 | 51.511 | 43.624 | 18.08% |
> | 5000 | 18.017 | 14.779 | 21.91% |

Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:

  change the type of i in for loop to match the type of unroll

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/36/files
  - new: https://git.openjdk.java.net/riscv-port/pull/36/files/90816db0..620dcde8

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=36&range=01
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=36&range=00-01

  Stats: 1 line in 1 file changed: 0 ins; 0 del; 1 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/36.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/36/head:pull/36

PR: https://git.openjdk.java.net/riscv-port/pull/36

From duke at openjdk.java.net  Tue Dec 21 09:06:26 2021
From: duke at openjdk.java.net (guotaiping1)
Date: Tue, 21 Dec 2021 09:06:26 GMT
Subject: [riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd [v2]
In-Reply-To: <5DndLzTjseGU3H1rJtv3ypkvkQUSNZkiaIvhSgcMkd4=.280cc590-7766-4faf-8b0b-514212a3d4ee@github.com>
References: <TakqWYumLto3fsFenakfk5QRKi7-0sVfIazl3Wjka7Y=.5cf6ee76-8924-4f89-85ef-49bc53268f8e@github.com>
 <5DndLzTjseGU3H1rJtv3ypkvkQUSNZkiaIvhSgcMkd4=.280cc590-7766-4faf-8b0b-514212a3d4ee@github.com>
Message-ID: <DUTLQrdrsrhzUAsIPD49-B6uZkBb6HpD5GK1BM9rdZ0=.f6f65261-05f9-4f97-850a-7511a80996e7@github.com>

On Tue, 21 Dec 2021 08:40:30 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   change the type of i in for loop to match the type of unroll
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3049:
> 
>> 3047:                              Register len, Register k, Register tmp) {
>> 3048:   Label L_tail_loop, L_unroll, L_end;
>> 3049:   mv(tmp, out);
> 
> I think this "mv" instruction could be moved after the zero check for"len". Then we will save one instruction when "len" is zero.

Thanks for your review, but if the `mv(tmp, out)` instruction is moved after `beqz(len, L_end)`, the `tmp` in `add(offset, tmp, t0)` is not as expected because of the `mv(out, zr)` before `beqz(len, L_end)`.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/36

From fjiang at openjdk.java.net  Tue Dec 21 09:06:27 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Tue, 21 Dec 2021 09:06:27 GMT
Subject: [riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd [v2]
In-Reply-To: <5DndLzTjseGU3H1rJtv3ypkvkQUSNZkiaIvhSgcMkd4=.280cc590-7766-4faf-8b0b-514212a3d4ee@github.com>
References: <TakqWYumLto3fsFenakfk5QRKi7-0sVfIazl3Wjka7Y=.5cf6ee76-8924-4f89-85ef-49bc53268f8e@github.com>
 <5DndLzTjseGU3H1rJtv3ypkvkQUSNZkiaIvhSgcMkd4=.280cc590-7766-4faf-8b0b-514212a3d4ee@github.com>
Message-ID: <MsSYl6DmYAeKHArX_Rw36iLGivQRfucUsBNEoRKHuSU=.79f50c8d-ce21-4061-9092-4e60bdb3349c@github.com>

On Tue, 21 Dec 2021 08:41:46 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   change the type of i in for loop to match the type of unroll
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3062:
> 
>> 3060:   blt(len, tmp, L_tail_loop);
>> 3061:   bind(L_unroll);
>> 3062:   for (unsigned i = 0; i < unroll; i++) {
> 
> Better to change type of "i" into signed, i.e., "for (int i = 0; i < unroll; i++)"

Thanks, the type of `i` is the same as `unroll` now.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/36

From fyang at openjdk.java.net  Tue Dec 21 09:10:40 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Tue, 21 Dec 2021 09:10:40 GMT
Subject: [riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd [v2]
In-Reply-To: <jtLCTBpSoVPXQZk4ZsyvS_OHFf7iJfrhceDoMNyFk1A=.610a5fa8-0945-421b-84de-490e847ba5d7@github.com>
References: <TakqWYumLto3fsFenakfk5QRKi7-0sVfIazl3Wjka7Y=.5cf6ee76-8924-4f89-85ef-49bc53268f8e@github.com>
 <jtLCTBpSoVPXQZk4ZsyvS_OHFf7iJfrhceDoMNyFk1A=.610a5fa8-0945-421b-84de-490e847ba5d7@github.com>
Message-ID: <qDORJbR6Ibi78fTpcf4fOMdQkpJmYpj5NSeh810zN1g=.faaedda5-f344-4777-8e06-172bc94a2068@github.com>

On Tue, 21 Dec 2021 09:06:25 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> BigInteger intrinsic: mulAdd intrinsic is missed in current vm. It should be implemented.
>> The JMH test of mulAdd intrinsic on the matched board shows that the performance can be improved by 0.69%~21.91% when the length of BigInteger changed from 1 to 5000, compared with that of C2.
>> JMH test: [MyBenchmark.java](https://bugs.openjdk.java.net/secure/attachment/97414/MyBenchmark.java)
>> 
>> Performed full jtreg test with qemu without new failures.
>> 
>> Results list as follows
>> | length | intrinsic(ops/ms) | no intrinsic(ops/ms) | intrinsic / no intrinsic |
>> | ------ | ------ | ------ | ------ | 
>> | 1 | 1643.111 | 1623.814 | 1.18% |
>> | 2 | 1597.927 | 1585.216 | 0.80% |
>> | 3 | 1542.249 | 1502.455 | 2.65% |
>> | 5 | 1533.371 | 1522.837 | 0.69% |
>> | 10 | 1377.683 | 1361.718 | 1.17% |
>> | 50 | 925.826 | 844.276 | 9.62% |
>> | 100 | 638.767 | 576.276 | 10.84% |
>> | 1000 | 99.870 | 84.796 | 17.78% |
>> | 2000 | 51.511 | 43.624 | 18.08% |
>> | 5000 | 18.017 | 14.779 | 21.91% |
>
> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   change the type of i in for loop to match the type of unroll

Looks good. Thanks.

-------------

Marked as reviewed by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/36

From fyang at openjdk.java.net  Tue Dec 21 09:10:43 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Tue, 21 Dec 2021 09:10:43 GMT
Subject: [riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd [v2]
In-Reply-To: <DUTLQrdrsrhzUAsIPD49-B6uZkBb6HpD5GK1BM9rdZ0=.f6f65261-05f9-4f97-850a-7511a80996e7@github.com>
References: <TakqWYumLto3fsFenakfk5QRKi7-0sVfIazl3Wjka7Y=.5cf6ee76-8924-4f89-85ef-49bc53268f8e@github.com>
 <5DndLzTjseGU3H1rJtv3ypkvkQUSNZkiaIvhSgcMkd4=.280cc590-7766-4faf-8b0b-514212a3d4ee@github.com>
 <DUTLQrdrsrhzUAsIPD49-B6uZkBb6HpD5GK1BM9rdZ0=.f6f65261-05f9-4f97-850a-7511a80996e7@github.com>
Message-ID: <xp2dzWkvxAVufPTAN5hDBea8k144yxQQwhcJeibGbRo=.84d48d4a-d023-4739-a4eb-5ef2e21cf8fa@github.com>

On Tue, 21 Dec 2021 09:01:33 GMT, guotaiping1 <duke at openjdk.java.net> wrote:

>> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3049:
>> 
>>> 3047:                              Register len, Register k, Register tmp) {
>>> 3048:   Label L_tail_loop, L_unroll, L_end;
>>> 3049:   mv(tmp, out);
>> 
>> I think this "mv" instruction could be moved after the zero check for"len". Then we will save one instruction when "len" is zero.
>
> Thanks for your review, but if the `mv(tmp, out)` instruction is moved after `beqz(len, L_end)`, the `tmp` in `add(offset, tmp, t0)` is not as expected because of the `mv(out, zr)` before `beqz(len, L_end)`.

Yes, you are right. I didn't notice that.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/36

From fjiang at openjdk.java.net  Tue Dec 21 09:17:42 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Tue, 21 Dec 2021 09:17:42 GMT
Subject: [riscv-port] Integrated: 8278644: riscv: Intrinsify mulAdd
In-Reply-To: <TakqWYumLto3fsFenakfk5QRKi7-0sVfIazl3Wjka7Y=.5cf6ee76-8924-4f89-85ef-49bc53268f8e@github.com>
References: <TakqWYumLto3fsFenakfk5QRKi7-0sVfIazl3Wjka7Y=.5cf6ee76-8924-4f89-85ef-49bc53268f8e@github.com>
Message-ID: <cFzz3NtvtUDDGNk45gkmfSp13FhpsfPLWJ4X-UcDDF4=.689bbb5d-7255-4728-add1-a826bb635734@github.com>

On Tue, 21 Dec 2021 01:15:43 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> BigInteger intrinsic: mulAdd intrinsic is missed in current vm. It should be implemented.
> The JMH test of mulAdd intrinsic on the matched board shows that the performance can be improved by 0.69%~21.91% when the length of BigInteger changed from 1 to 5000, compared with that of C2.
> JMH test: [MyBenchmark.java](https://bugs.openjdk.java.net/secure/attachment/97414/MyBenchmark.java)
> 
> Performed full jtreg test with qemu without new failures.
> 
> Results list as follows
> | length | intrinsic(ops/ms) | no intrinsic(ops/ms) | intrinsic / no intrinsic |
> | ------ | ------ | ------ | ------ | 
> | 1 | 1643.111 | 1623.814 | 1.18% |
> | 2 | 1597.927 | 1585.216 | 0.80% |
> | 3 | 1542.249 | 1502.455 | 2.65% |
> | 5 | 1533.371 | 1522.837 | 0.69% |
> | 10 | 1377.683 | 1361.718 | 1.17% |
> | 50 | 925.826 | 844.276 | 9.62% |
> | 100 | 638.767 | 576.276 | 10.84% |
> | 1000 | 99.870 | 84.796 | 17.78% |
> | 2000 | 51.511 | 43.624 | 18.08% |
> | 5000 | 18.017 | 14.779 | 21.91% |

This pull request has now been integrated.

Changeset: 6247be12
Author:    Feilong Jiang <fjiang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/6247be12fea3b1e8ca5498f13c1ad3b0488eb34f
Stats:     106 lines in 4 files changed: 106 ins; 0 del; 0 mod

8278644: riscv: Intrinsify mulAdd

Co-authored-by: Taiping Guo <guotaiping1 at huawei.com>
Reviewed-by: fyang

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/36

From duke at openjdk.java.net  Wed Dec 22 06:32:39 2021
From: duke at openjdk.java.net (duke)
Date: Wed, 22 Dec 2021 06:32:39 GMT
Subject: git: openjdk/riscv-port: riscv-port: 39 new changesets
Message-ID: <ce36acdf-c1ef-465d-aa8b-aaaeebc488a8@openjdk.java.net>

Changeset: 31fbb872
Author:    TejeshR13 <tejesh.r at oracle.com>
Committer: Jayathirth D V <jdv at openjdk.org>
Date:      2021-12-20 09:53:22 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/31fbb8723e973d4217c80cccba90b2dceb6fa792

6462028: MaskFormatter API documentation refers to getDisplayValue

Reviewed-by: psadhukhan, aivanov, prr

! src/java.desktop/share/classes/javax/swing/text/MaskFormatter.java

Changeset: 06206c71
Author:    Roland Westrelin <roland at openjdk.org>
Date:      2021-12-20 10:00:14 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/06206c7199e9b49382d5f489ed5733525a95a535

8278949: Cleanups for 8277850

Co-authored-by: John R Rose <jrose at openjdk.org>
Reviewed-by: kvn, jrose

! src/hotspot/share/opto/mulnode.cpp
! src/hotspot/share/opto/mulnode.hpp
! test/hotspot/jtreg/compiler/c2/irTests/TestShiftAndMask.java

Changeset: 4c78c9ab
Author:    David Holmes <dholmes at openjdk.org>
Date:      2021-12-20 10:47:37 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/4c78c9ab80202b426efd8f6cc3533d642ae9ba19

8270929: Obsolete the FilterSpuriousWakeups flag in JDK 19

Reviewed-by: hseigel, rehn

! src/hotspot/os/posix/os_posix.cpp
! src/hotspot/share/runtime/arguments.cpp
! src/hotspot/share/runtime/globals.hpp

Changeset: 8549d8b5
Author:    Calvin Cheung <ccheung at openjdk.org>
Date:      2021-12-20 23:04:40 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8549d8b5697606ef87bb3f72abcf14dd7eb8a151

8277100: Dynamic dump can inadvertently overwrite default CDS archive

Reviewed-by: iklam, minqi, dholmes

! src/hotspot/share/runtime/arguments.cpp
+ test/hotspot/jtreg/runtime/cds/appcds/dynamicArchive/DumpToDefaultArchive.java

Changeset: 51796728
Author:    Joe Darcy <darcy at openjdk.org>
Date:      2021-12-21 00:25:56 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/517967284cf607c0137e088a33ab5eb98d59542d

8278953: Clarify Class.getDeclaredConstructor specification

Reviewed-by: mchung, alanb

! src/java.base/share/classes/java/lang/Class.java

Changeset: ff5d4176
Author:    Thomas Schatzl <tschatzl at openjdk.org>
Date:      2021-12-21 09:51:21 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ff5d41762d5ba31e88c6cb9207a8ae57f34a69b0

8278893: Parallel: Remove GCWorkerDelayMillis

Reviewed-by: ayang, mli

! src/hotspot/share/gc/parallel/parallel_globals.hpp
! src/hotspot/share/gc/parallel/psCardTable.cpp
! src/hotspot/share/gc/parallel/psPromotionManager.inline.hpp

Changeset: 29bd7363
Author:    Aleksey Shipilev <shade at openjdk.org>
Date:      2021-12-21 14:01:47 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/29bd73638a22d341767a1266723a7d7263e17093

8277893: Arraycopy stress tests

Reviewed-by: kvn, mli

! test/hotspot/jtreg/TEST.groups
+ test/hotspot/jtreg/compiler/arraycopy/stress/AbstractStressArrayCopy.java
+ test/hotspot/jtreg/compiler/arraycopy/stress/StressBooleanArrayCopy.java
+ test/hotspot/jtreg/compiler/arraycopy/stress/StressByteArrayCopy.java
+ test/hotspot/jtreg/compiler/arraycopy/stress/StressCharArrayCopy.java
+ test/hotspot/jtreg/compiler/arraycopy/stress/StressDoubleArrayCopy.java
+ test/hotspot/jtreg/compiler/arraycopy/stress/StressFloatArrayCopy.java
+ test/hotspot/jtreg/compiler/arraycopy/stress/StressIntArrayCopy.java
+ test/hotspot/jtreg/compiler/arraycopy/stress/StressLongArrayCopy.java
+ test/hotspot/jtreg/compiler/arraycopy/stress/StressObjectArrayCopy.java
+ test/hotspot/jtreg/compiler/arraycopy/stress/StressShortArrayCopy.java
+ test/hotspot/jtreg/compiler/arraycopy/stress/TestStressArrayCopy.java

Changeset: f4f2f32c
Author:    Stefan Johansson <sjohanss at openjdk.org>
Date:      2021-12-21 14:03:08 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f4f2f32cd16158d8d4d2b552cd74531f25c45a29

8278917: Use Prev Bitmap for recording evac failed objects

Reviewed-by: ayang, mli, tschatzl

! src/hotspot/share/gc/g1/g1CollectedHeap.cpp
! src/hotspot/share/gc/g1/g1CollectedHeap.hpp
! src/hotspot/share/gc/g1/g1CollectedHeap.inline.hpp
! src/hotspot/share/gc/g1/g1ConcurrentMark.hpp
! src/hotspot/share/gc/g1/g1ConcurrentMark.inline.hpp
! src/hotspot/share/gc/g1/g1EvacFailure.cpp
- src/hotspot/share/gc/g1/g1EvacFailureObjectsSet.cpp
- src/hotspot/share/gc/g1/g1EvacFailureObjectsSet.hpp
- src/hotspot/share/gc/g1/g1EvacFailureObjectsSet.inline.hpp
! src/hotspot/share/gc/g1/g1FullGCCompactTask.cpp
! src/hotspot/share/gc/g1/g1FullGCCompactTask.hpp
! src/hotspot/share/gc/g1/g1ParScanThreadState.cpp
! src/hotspot/share/gc/g1/g1RemSet.cpp
! src/hotspot/share/gc/g1/heapRegion.cpp
! src/hotspot/share/gc/g1/heapRegion.hpp
! src/hotspot/share/gc/g1/heapRegion.inline.hpp

Changeset: f90425a1
Author:    Roger Riggs <rriggs at openjdk.org>
Date:      2021-12-21 14:24:44 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f90425a1cbbc686045c87086af586e62f05f6c49

8278087: Deserialization filter and filter factory property error reporting under specified

Reviewed-by: lancea, bpb

! src/java.base/share/classes/java/io/ObjectInputFilter.java
! src/java.base/share/classes/java/io/ObjectInputStream.java
! test/jdk/java/io/Serializable/serialFilter/InvalidGlobalFilterTest.java
! test/jdk/java/io/Serializable/serialFilter/SerialFactoryFaults.java

Changeset: 8c0bb53f
Author:    Roger Riggs <rriggs at openjdk.org>
Date:      2021-12-21 15:16:19 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8c0bb53f5ba6e71b81c9cb99e6f1587150fe531a

8278044: ObjectInputStream methods invoking the OIF.CFG.getSerialFilterFactory() silent about error cases.

Reviewed-by: lancea, bpb

! src/java.base/share/classes/java/io/ObjectInputStream.java

Changeset: f7309060
Author:    Robbin Ehn <rehn at openjdk.org>
Date:      2021-12-21 16:12:32 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f7309060ded0edb1e614663572f876d83b77c28e

8278793: Interpreter(x64) intrinsify Thread.currentThread()

Reviewed-by: rkennke, dcubed, dholmes

! src/hotspot/cpu/x86/gc/shenandoah/shenandoahBarrierSetAssembler_x86.cpp
! src/hotspot/cpu/x86/templateInterpreterGenerator_x86_64.cpp
! src/hotspot/share/interpreter/abstractInterpreter.cpp
! src/hotspot/share/interpreter/abstractInterpreter.hpp
! src/hotspot/share/interpreter/templateInterpreterGenerator.cpp
! src/hotspot/share/interpreter/templateInterpreterGenerator.hpp

Changeset: f31dead6
Author:    Daniel Jelinski <djelinski1 at gmail.com>
Committer: Weijun Wang <weijun at openjdk.org>
Date:      2021-12-21 18:24:31 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f31dead6c550444a836655ffdf97df8816e2d546

8279043: Some Security Exception Messages Miss Spaces

Reviewed-by: weijun

! src/java.base/share/classes/com/sun/crypto/provider/GaloisCounterMode.java
! src/java.base/share/classes/com/sun/crypto/provider/TlsKeyMaterialGenerator.java
! src/java.base/share/classes/javax/crypto/Cipher.java
! src/java.base/share/classes/sun/security/pkcs/PKCS9Attribute.java
! src/java.base/share/classes/sun/security/pkcs12/PKCS12KeyStore.java
! src/java.base/share/classes/sun/security/rsa/RSAPadding.java
! src/java.base/share/classes/sun/security/ssl/CertificateAuthoritiesExtension.java
! src/java.base/share/classes/sun/security/util/DisabledAlgorithmConstraints.java
! src/java.base/share/classes/sun/security/x509/PolicyConstraintsExtension.java
! src/java.base/share/classes/sun/security/x509/PolicyInformation.java
! src/java.security.jgss/share/classes/sun/security/jgss/krb5/Krb5MechFactory.java
! test/jdk/com/sun/crypto/provider/Cipher/AEAD/GCMBufferTest.java
! test/jdk/com/sun/crypto/provider/Cipher/AEAD/GCMShortBuffer.java
! test/jdk/sun/security/provider/PolicyParser/PrincipalExpansionError.java
! test/jdk/sun/security/ssl/X509TrustManagerImpl/CacertsLimit.java
! test/jdk/sun/security/tools/keytool/fakegen/jdk.crypto.ec/sun/security/ec/ECKeyPairGenerator.java

Changeset: 6aeb40cf
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-12-21 20:49:59 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/6aeb40cf2a5cfc827797cd1321c8d96f36ef4f1d

8278396: G1: Initialize the BOT threshold to be region bottom

Reviewed-by: tschatzl, sjohanss

! src/hotspot/share/gc/g1/g1BlockOffsetTable.cpp
! src/hotspot/share/gc/g1/g1BlockOffsetTable.hpp
! src/hotspot/share/gc/g1/heapRegion.cpp

Changeset: 997b1eea
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-12-21 20:50:46 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/997b1eea6e3c572f905f88f3f5b047a5aa180d1e

8279060: Parallel: Remove unused PSVirtualSpace constructors

Reviewed-by: mli, sjohanss, tschatzl

! src/hotspot/share/gc/parallel/psVirtualspace.cpp
! src/hotspot/share/gc/parallel/psVirtualspace.hpp

Changeset: f5d7c777
Author:    Mark Reinhold <mr at openjdk.org>
Date:      2021-12-17 00:34:03 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f5d7c777bc516fa2e711c19d5281ebf32384b543

8276826: Clarify the ModuleDescriptor.Version specification?s treatment of repeated punctuation characters

Reviewed-by: mchung, darcy

! src/java.base/share/classes/java/lang/module/ModuleDescriptor.java

Changeset: 8494fec6
Author:    Jatin Bhateja <jbhateja at openjdk.org>
Date:      2021-12-17 03:07:08 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8494fec665bfa51d1702827bd0aa4f4547e67729

8278796: Incorrect behavior of FloatVector.withLane on X86

Reviewed-by: sviswanathan, kvn

! src/hotspot/cpu/x86/x86.ad
! test/jdk/jdk/incubator/vector/Byte128VectorTests.java
! test/jdk/jdk/incubator/vector/Byte256VectorTests.java
! test/jdk/jdk/incubator/vector/Byte512VectorTests.java
! test/jdk/jdk/incubator/vector/Byte64VectorTests.java
! test/jdk/jdk/incubator/vector/ByteMaxVectorTests.java
! test/jdk/jdk/incubator/vector/Double128VectorTests.java
! test/jdk/jdk/incubator/vector/Double256VectorTests.java
! test/jdk/jdk/incubator/vector/Double512VectorTests.java
! test/jdk/jdk/incubator/vector/Double64VectorTests.java
! test/jdk/jdk/incubator/vector/DoubleMaxVectorTests.java
! test/jdk/jdk/incubator/vector/Float128VectorTests.java
! test/jdk/jdk/incubator/vector/Float256VectorTests.java
! test/jdk/jdk/incubator/vector/Float512VectorTests.java
! test/jdk/jdk/incubator/vector/Float64VectorTests.java
! test/jdk/jdk/incubator/vector/FloatMaxVectorTests.java
! test/jdk/jdk/incubator/vector/Int128VectorTests.java
! test/jdk/jdk/incubator/vector/Int256VectorTests.java
! test/jdk/jdk/incubator/vector/Int512VectorTests.java
! test/jdk/jdk/incubator/vector/Int64VectorTests.java
! test/jdk/jdk/incubator/vector/IntMaxVectorTests.java
! test/jdk/jdk/incubator/vector/Long128VectorTests.java
! test/jdk/jdk/incubator/vector/Long256VectorTests.java
! test/jdk/jdk/incubator/vector/Long512VectorTests.java
! test/jdk/jdk/incubator/vector/Long64VectorTests.java
! test/jdk/jdk/incubator/vector/LongMaxVectorTests.java
! test/jdk/jdk/incubator/vector/Short128VectorTests.java
! test/jdk/jdk/incubator/vector/Short256VectorTests.java
! test/jdk/jdk/incubator/vector/Short512VectorTests.java
! test/jdk/jdk/incubator/vector/Short64VectorTests.java
! test/jdk/jdk/incubator/vector/ShortMaxVectorTests.java
! test/jdk/jdk/incubator/vector/templates/Kernel-With-Op.template
! test/jdk/jdk/incubator/vector/templates/Unit-With-Op.template
! test/jdk/jdk/incubator/vector/templates/Unit-header.template

Changeset: bb7efb35
Author:    Roland Westrelin <roland at openjdk.org>
Date:      2021-12-17 07:45:44 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/bb7efb3517b0ac66a55607c14aae3aef1f11c892

8278790: Inner loop of long loop nest runs for too few iterations

Reviewed-by: chagedorn, neliasso

! src/hotspot/share/opto/loopnode.cpp

Changeset: b9a477bf
Author:    Roland Westrelin <roland at openjdk.org>
Date:      2021-12-17 07:46:47 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/b9a477bf19d9f276f6b1da8984eb56d7bd5fc137

8275638: GraphKit::combine_exception_states fails with "matching stack sizes" assert

Reviewed-by: dlong, kvn

! src/hotspot/share/opto/callGenerator.cpp
! src/hotspot/share/opto/graphKit.cpp
+ test/hotspot/jtreg/compiler/exceptions/TestLateMHInlineExceptions.java

Changeset: fffa73c1
Author:    Erik Gahlin <egahlin at openjdk.org>
Date:      2021-12-17 09:49:44 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/fffa73c1ef377eb28371fc4094eea8725850de7d

8269425: 2 jdk/jfr/api/consumer/streaming tests failed to attach

Reviewed-by: mgronlun

! test/jdk/jdk/jfr/api/consumer/streaming/TestJVMCrash.java
! test/jdk/jdk/jfr/api/consumer/streaming/TestJVMExit.java
! test/lib/jdk/test/lib/jfr/StreamingUtils.java

Changeset: 9cd70906
Author:    Naoto Sato <naoto at openjdk.org>
Date:      2021-12-17 13:48:26 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/9cd709060cf0244ddb71225b55ea4e3e7f41860e

8278587: StringTokenizer(String, String, boolean) documentation bug

Backport-of: 8f5fdd864b6f1cf4a2d9d961d8d4118960f0751e

! src/java.base/share/classes/java/util/StringTokenizer.java

Changeset: b46f0b0b
Author:    Igor Veresov <iveresov at openjdk.org>
Date:      2021-12-17 16:30:40 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/b46f0b0b1f2ada705f8b5aac9b7d8423699437a1

8277447: Hotspot C1 compiler crashes on Kotlin suspend fun with loop

Reviewed-by: kvn, neliasso

! src/hotspot/share/c1/c1_Instruction.cpp
+ test/hotspot/jtreg/compiler/c1/TestC1PhiPlacementPathology.jasm
+ test/hotspot/jtreg/compiler/c1/TestC1PhiPlacementPathologyMain.java

Changeset: 8fbe1724
Author:    Artem Semenov <asemenov at openjdk.org>
Date:      2021-12-17 19:31:51 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8fbe1724e0f783132a65c45503addad9d98a329e

8278604: SwingSet2 table demo does not have accessible description set for images
8278526: [macos] Screen reader reads SwingSet2 JTable row selection as null, dimmed row for last column

Reviewed-by: ant, kizune, pbansal

! src/demo/share/jfc/SwingSet2/TableDemo.java

Changeset: a5f5d60f
Author:    Daniel D. Daugherty <dcubed at openjdk.org>
Date:      2021-12-17 21:24:51 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/a5f5d60f2529bb28eee6d309bfbde904e188e540

8273107: RunThese24H times out with "java.lang.management.ThreadInfo.getLockName()" is null

Reviewed-by: rehn, coleenp, eosterlund

! src/hotspot/share/runtime/monitorDeflationThread.cpp
! src/hotspot/share/runtime/synchronizer.cpp
! src/hotspot/share/runtime/synchronizer.hpp
! src/hotspot/share/runtime/vmOperations.cpp
! src/hotspot/share/runtime/vmOperations.hpp
! src/hotspot/share/services/heapDumper.cpp
! src/hotspot/share/services/threadService.cpp
! src/hotspot/share/services/threadService.hpp

Changeset: 36676db2
Author:    Alexander Matveev <almatvee at openjdk.org>
Date:      2021-12-17 21:56:55 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/36676db2fdb810f6d9fe7be8a81b86244dbdbf71

8278970: [macos] SigningPackageTest is failed with runtime exception

Reviewed-by: herrick, asemenyuk

! test/jdk/tools/jpackage/macosx/SigningPackageTest.java

Changeset: deaf75a5
Author:    Roland Westrelin <roland at openjdk.org>
Date:      2021-12-20 09:41:56 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/deaf75a58587f80046204de7559ff50b3b770bed

8278413: C2 crash when allocating array of size too large

Reviewed-by: neliasso, kvn

! src/hotspot/share/opto/callnode.cpp
! src/hotspot/share/opto/callnode.hpp
! src/hotspot/share/opto/cfgnode.cpp
! src/hotspot/share/opto/compile.cpp
! src/hotspot/share/opto/graphKit.cpp
! src/hotspot/share/opto/macro.cpp
! src/hotspot/share/opto/macro.hpp
! src/hotspot/share/opto/split_if.cpp
+ test/hotspot/jtreg/compiler/allocation/TestFailedAllocationBadGraph.java

Changeset: ad128284
Author:    Aleksandr Veselov <aleksandr.veselov at jetbrains.com>
Committer: Anton Tarasov <ant at openjdk.org>
Date:      2021-12-20 11:40:58 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ad1282842c5eefdad151afe6f4db97a09d643546

8278609: [macos] accessibility frame is misplaced on a secondary monitor on macOS

Reviewed-by: ant, kizune

! src/java.desktop/macosx/native/libawt_lwawt/awt/a11y/CommonComponentAccessibility.m

Changeset: 819f9bd0
Author:    Smita Kamath <svkamath at openjdk.org>
Committer: Sandhya Viswanathan <sviswanathan at openjdk.org>
Date:      2021-12-20 20:09:42 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/819f9bd084fa49222a4310fbcf4933005e9f0ca4

8274323: compiler/codegen/aes/TestAESMain.java failed with "Error: invalid offset: -1434443640" after 8273297

Reviewed-by: sviswanathan, kvn

! src/hotspot/cpu/aarch64/matcher_aarch64.hpp
! src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp
! src/hotspot/cpu/arm/matcher_arm.hpp
! src/hotspot/cpu/ppc/matcher_ppc.hpp
! src/hotspot/cpu/s390/matcher_s390.hpp
! src/hotspot/cpu/x86/matcher_x86.hpp
! src/hotspot/cpu/x86/stubGenerator_x86_64.cpp
! src/hotspot/share/opto/graphKit.cpp
! src/hotspot/share/opto/graphKit.hpp
! src/hotspot/share/opto/library_call.cpp
! src/hotspot/share/opto/runtime.cpp
! test/hotspot/jtreg/ProblemList-Xcomp.txt

Changeset: 467f6549
Author:    Aleksey Shipilev <shade at openjdk.org>
Date:      2021-12-21 12:33:59 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/467f654916764751746934f80877d49a5f107194

8279011: JFR: JfrChunkWriter incorrectly handles int64_t chunk size as size_t

Reviewed-by: mgronlun

! src/hotspot/share/jfr/recorder/repository/jfrChunkWriter.cpp

Changeset: db3d6d77
Author:    Roger Riggs <rriggs at openjdk.org>
Date:      2021-12-21 15:42:36 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/db3d6d772411c4e7bc81d6411abb139462e1581f

8278087: Deserialization filter and filter factory property error reporting under specified

Backport-of: f90425a1cbbc686045c87086af586e62f05f6c49

! src/java.base/share/classes/java/io/ObjectInputFilter.java
! src/java.base/share/classes/java/io/ObjectInputStream.java
! test/jdk/java/io/Serializable/serialFilter/InvalidGlobalFilterTest.java
! test/jdk/java/io/Serializable/serialFilter/SerialFactoryFaults.java

Changeset: ac7430cf
Author:    Roger Riggs <rriggs at openjdk.org>
Date:      2021-12-21 16:31:58 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ac7430cf7efba519c1fd8b1c1b23136bf158f19f

8278044: ObjectInputStream methods invoking the OIF.CFG.getSerialFilterFactory() silent about error cases.

Backport-of: 8c0bb53f5ba6e71b81c9cb99e6f1587150fe531a

! src/java.base/share/classes/java/io/ObjectInputStream.java

Changeset: 54517fa3
Author:    Daniel D. Daugherty <dcubed at openjdk.org>
Date:      2021-12-21 17:42:26 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/54517fa3d80b50bfa8a4f6b7937b95e379a1dfeb

8279074: ProblemList compiler/codecache/jmx/PoolsIndependenceTest.java on macosx-aarch64

Reviewed-by: ccheung

! test/hotspot/jtreg/ProblemList.txt

Changeset: 1128674d
Author:    Zhengyu Gu <zgu at openjdk.org>
Date:      2021-12-21 19:02:01 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/1128674d7f3766dda8869b213e1fc629e44ea7a8

8278627: Shenandoah: TestHeapDump test failed

Reviewed-by: shade, rkennke

! src/hotspot/share/gc/shenandoah/shenandoahClosures.inline.hpp
! src/hotspot/share/gc/shenandoah/shenandoahRootProcessor.cpp
! src/hotspot/share/gc/shenandoah/shenandoahRootProcessor.hpp

Changeset: 803cb8a7
Author:    Jesper Wilhelmsson <jwilhelm at openjdk.org>
Date:      2021-12-21 21:58:05 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/803cb8a76827a21fcf9e033b4ca6a777c509169b

Merge

! src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp
! src/hotspot/cpu/x86/x86.ad
! src/hotspot/share/c1/c1_Instruction.cpp
! src/hotspot/share/gc/shenandoah/shenandoahRootProcessor.cpp
! src/hotspot/share/gc/shenandoah/shenandoahRootProcessor.hpp
! src/hotspot/share/opto/compile.cpp
! src/hotspot/share/opto/library_call.cpp
! test/jdk/jdk/incubator/vector/Byte128VectorTests.java
! test/jdk/jdk/incubator/vector/Byte256VectorTests.java
! test/jdk/jdk/incubator/vector/Byte512VectorTests.java
! test/jdk/jdk/incubator/vector/Byte64VectorTests.java
! test/jdk/jdk/incubator/vector/Double128VectorTests.java
! test/jdk/jdk/incubator/vector/Double256VectorTests.java
! test/jdk/jdk/incubator/vector/Double512VectorTests.java
! test/jdk/jdk/incubator/vector/Double64VectorTests.java
! test/jdk/jdk/incubator/vector/Float128VectorTests.java
! test/jdk/jdk/incubator/vector/Float256VectorTests.java
! test/jdk/jdk/incubator/vector/Float512VectorTests.java
! test/jdk/jdk/incubator/vector/Float64VectorTests.java
! test/jdk/jdk/incubator/vector/Int128VectorTests.java
! test/jdk/jdk/incubator/vector/Int256VectorTests.java
! test/jdk/jdk/incubator/vector/Int512VectorTests.java
! test/jdk/jdk/incubator/vector/Int64VectorTests.java
! test/jdk/jdk/incubator/vector/Long128VectorTests.java
! test/jdk/jdk/incubator/vector/Long256VectorTests.java
! test/jdk/jdk/incubator/vector/Long512VectorTests.java
! test/jdk/jdk/incubator/vector/Long64VectorTests.java
! test/jdk/jdk/incubator/vector/Short128VectorTests.java
! test/jdk/jdk/incubator/vector/Short256VectorTests.java
! test/jdk/jdk/incubator/vector/Short512VectorTests.java
! test/jdk/jdk/incubator/vector/Short64VectorTests.java
! src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp
! src/hotspot/cpu/x86/x86.ad
! src/hotspot/share/c1/c1_Instruction.cpp
! src/hotspot/share/gc/shenandoah/shenandoahRootProcessor.cpp
! src/hotspot/share/gc/shenandoah/shenandoahRootProcessor.hpp
! src/hotspot/share/opto/compile.cpp
! src/hotspot/share/opto/library_call.cpp
! test/jdk/jdk/incubator/vector/Byte128VectorTests.java
! test/jdk/jdk/incubator/vector/Byte256VectorTests.java
! test/jdk/jdk/incubator/vector/Byte512VectorTests.java
! test/jdk/jdk/incubator/vector/Byte64VectorTests.java
! test/jdk/jdk/incubator/vector/Double128VectorTests.java
! test/jdk/jdk/incubator/vector/Double256VectorTests.java
! test/jdk/jdk/incubator/vector/Double512VectorTests.java
! test/jdk/jdk/incubator/vector/Double64VectorTests.java
! test/jdk/jdk/incubator/vector/Float128VectorTests.java
! test/jdk/jdk/incubator/vector/Float256VectorTests.java
! test/jdk/jdk/incubator/vector/Float512VectorTests.java
! test/jdk/jdk/incubator/vector/Float64VectorTests.java
! test/jdk/jdk/incubator/vector/Int128VectorTests.java
! test/jdk/jdk/incubator/vector/Int256VectorTests.java
! test/jdk/jdk/incubator/vector/Int512VectorTests.java
! test/jdk/jdk/incubator/vector/Int64VectorTests.java
! test/jdk/jdk/incubator/vector/Long128VectorTests.java
! test/jdk/jdk/incubator/vector/Long256VectorTests.java
! test/jdk/jdk/incubator/vector/Long512VectorTests.java
! test/jdk/jdk/incubator/vector/Long64VectorTests.java
! test/jdk/jdk/incubator/vector/Short128VectorTests.java
! test/jdk/jdk/incubator/vector/Short256VectorTests.java
! test/jdk/jdk/incubator/vector/Short512VectorTests.java
! test/jdk/jdk/incubator/vector/Short64VectorTests.java

Changeset: fb623f1d
Author:    Weijun Wang <weijun at openjdk.org>
Date:      2021-12-21 22:13:04 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/fb623f1d2ee858fbc6edfeaaa702b5fcd832a0aa

8279066: entries.remove(entry) is useless in PKCS12KeyStore

Reviewed-by: mullan

! src/java.base/share/classes/sun/security/pkcs12/PKCS12KeyStore.java

Changeset: 00c0d108
Author:    Chris Plummer <cjplummer at openjdk.org>
Date:      2021-12-21 22:55:09 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/00c0d1087021603f3f09131cb0458ac8b9c110e5

8244670: convert clhsdb "whatis" command from javascript to java

Reviewed-by: sspitsyn, kevinw

! src/jdk.hotspot.agent/doc/clhsdb.html
! src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/CommandProcessor.java
! test/hotspot/jtreg/serviceability/sa/ClhsdbFindPC.java

Changeset: 84d3333c
Author:    Daniel D. Daugherty <dcubed at openjdk.org>
Date:      2021-12-21 20:39:06 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/84d3333c7a979742021e759766a7290539b569f4

8279081: ProblemList jdk/jfr/event/oldobject/TestLargeRootSet.java on 2 platforms

Reviewed-by: azvegint, sspitsyn

! test/jdk/ProblemList.txt

Changeset: bf282649
Author:    Jesper Wilhelmsson <jwilhelm at openjdk.org>
Date:      2021-12-21 23:07:35 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/bf2826499a26363d01a5269bd2f54e9c363d4cdc

Merge


Changeset: d0ea7c9d
Author:    Chris Plummer <cjplummer at openjdk.org>
Date:      2021-12-22 03:56:08 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/d0ea7c9db9cc9ce80b60c2f94c53bb307792fc51

8279024: Remove javascript references from clhsdb.html

Reviewed-by: kevinw, sspitsyn

! src/jdk.hotspot.agent/doc/clhsdb.html
! src/jdk.hotspot.agent/doc/index.html

Changeset: 597049c3
Author:    Fei Yang <felix.yang at huawei.com>
Date:      2021-12-22 01:27:04 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/597049c3621c692a2250c0c4e42968913b75074c

Merge branch 'master' into riscv-port

! src/hotspot/cpu/riscv/matcher_riscv.hpp
! src/hotspot/cpu/riscv/riscv.ad
! src/hotspot/cpu/riscv/stubGenerator_riscv.cpp
! src/hotspot/share/runtime/arguments.cpp
! src/hotspot/share/runtime/synchronizer.cpp
+ src/hotspot/cpu/riscv/matcher_riscv.hpp
+ src/hotspot/cpu/riscv/riscv.ad
+ src/hotspot/cpu/riscv/stubGenerator_riscv.cpp
! src/hotspot/share/runtime/arguments.cpp
! src/hotspot/share/runtime/synchronizer.cpp


From xlinzheng at openjdk.java.net  Thu Dec 23 06:39:38 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Thu, 23 Dec 2021 06:39:38 GMT
Subject: [riscv-port] RFR: 8278994: riscv: RVC: basic instruction set
In-Reply-To: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
References: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
Message-ID: <uGwwj1yHrpnfXuqcTkG7s6JLn75YGPLZ-A_LVH9U6XA=.23f4800a-9223-4177-9ef3-c76aa5169519@github.com>

On Mon, 20 Dec 2021 08:10:10 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
> 
> This patch includes the basic definition of the RVC instruction set and some cleanups. Tested a simple `test/hotspot/jtreg/compiler/` folder on qemu.
> 
> Thanks,
> Xiaolin

I have discussed with Yadong and we may hold the optional `RVC_Assembler` implementation temporarily. This will not affect the `CompressibleRegion` implementation so please feel safe. Now this patch might be ready to review because it seems less possible to change in design, and thank you for your patience.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/34

From duke at openjdk.java.net  Fri Dec 24 02:08:20 2021
From: duke at openjdk.java.net (duke)
Date: Fri, 24 Dec 2021 02:08:20 GMT
Subject: git: openjdk/riscv-port: riscv-port: 31 new changesets
Message-ID: <c974cbfc-f906-49ef-9008-5a6ef6f2e0cd@openjdk.java.net>

Changeset: 3f41fdec
Author:    Albert Mingkun Yang <ayang at openjdk.org>
Date:      2021-12-22 13:44:20 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/3f41fdecdb6d131a5afe6e0a39d7414c222fe4fb

8279063: Consolidate push and push_if_necessary in PreservedMarks

Reviewed-by: rkennke, mli, tschatzl

! src/hotspot/share/gc/g1/g1FullGCMarker.inline.hpp
! src/hotspot/share/gc/shared/preservedMarks.hpp
! src/hotspot/share/gc/shared/preservedMarks.inline.hpp
! test/hotspot/gtest/gc/shared/test_preservedMarks.cpp

Changeset: a6903f80
Author:    Yumin Qi <minqi at openjdk.org>
Date:      2021-12-22 16:14:59 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/a6903f806a9071b2c6c4dbb190b0041867e5bb80

8279018: CRC calculation in CDS should not include _version and _head_size

Reviewed-by: iklam, ccheung

! src/hotspot/share/cds/filemap.cpp
! src/hotspot/share/include/cds.h
! src/hotspot/share/prims/whitebox.cpp
! test/hotspot/jtreg/runtime/cds/appcds/SharedArchiveConsistency.java
! test/lib/jdk/test/lib/cds/CDSArchiveUtils.java
! test/lib/jdk/test/whitebox/WhiteBox.java
! test/lib/sun/hotspot/WhiteBox.java

Changeset: 9a478b34
Author:    Yumin Qi <minqi at openjdk.org>
Date:      2021-12-22 16:17:33 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/9a478b347e1ef7aecfc8bbc2e3c5e6ac7c23ba36

8279022: JCmdTestFileSafety.java should check file time stamp for test result

Reviewed-by: ccheung

! test/hotspot/jtreg/runtime/cds/appcds/jcmd/JCmdTestFileSafety.java

Changeset: 9ee3ccfe
Author:    Smita Kamath <svkamath at openjdk.org>
Committer: Sandhya Viswanathan <sviswanathan at openjdk.org>
Date:      2021-12-21 22:09:43 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/9ee3ccfee2c9cc54ac7dca49fbf35135e627ef18

8279045: Intrinsics missing vzeroupper instruction

Reviewed-by: neliasso, sviswanathan, kvn

! src/hotspot/cpu/x86/stubGenerator_x86_64.cpp

Changeset: 97c5cd7f
Author:    Jatin Bhateja <jbhateja at openjdk.org>
Date:      2021-12-22 03:17:03 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/97c5cd7facf1d3565038c078d5688c7da15ad14e

8278508: Enable X86 maskAll instruction pattern for 32 bit JVM.

Reviewed-by: kvn, sviswanathan

! src/hotspot/cpu/x86/assembler_x86.cpp
! src/hotspot/cpu/x86/assembler_x86.hpp
! src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp
! src/hotspot/cpu/x86/c2_MacroAssembler_x86.hpp
! src/hotspot/cpu/x86/x86.ad
! src/hotspot/cpu/x86/x86_32.ad
! src/hotspot/cpu/x86/x86_64.ad
! test/jdk/jdk/incubator/vector/Byte512VectorTests.java
! test/jdk/jdk/incubator/vector/ByteMaxVectorTests.java
! test/jdk/jdk/incubator/vector/VectorReshapeTests.java

Changeset: 73414391
Author:    Kevin Walls <kevinw at openjdk.org>
Date:      2021-12-22 11:36:53 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/734143918de540382b5a0754bb7be1500b6f3596

8279007: jstatd fails to start because SecurityManager is disabled

Reviewed-by: alanb, sspitsyn, mullan

! make/modules/jdk.jstatd/Launcher.gmk
! test/jdk/sun/tools/jstatd/JstatdTest.java

Changeset: 713fbeb0
Author:    Markus Gr?nlund <mgronlun at openjdk.org>
Date:      2021-12-22 12:30:55 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/713fbeb050a8f79d3a662106125c3f14f3952741

8278987: RunThese24H.java failed with EXCEPTION_ACCESS_VIOLATION in __write_sample_info__

Reviewed-by: jbachorik

! src/hotspot/share/jfr/leakprofiler/checkpoint/objectSampleCheckpoint.cpp

Changeset: e49d4a98
Author:    Erik Gahlin <egahlin at openjdk.org>
Date:      2021-12-22 13:59:20 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/e49d4a9870c19f55a1d5473743880b415a8ead3c

8271447: java.nio.file.InvalidPathException: Malformed input or input contains unmappable characters

Reviewed-by: mgronlun

! src/jdk.jfr/share/classes/jdk/jfr/internal/management/ChunkFilename.java

Changeset: dfb15c3e
Author:    Erik Gahlin <egahlin at openjdk.org>
Date:      2021-12-22 14:29:46 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/dfb15c3e343974eb138ca1a8db3364cd2bac70a4

8274315: JFR: One closed state per file or stream

Reviewed-by: mgronlun

! src/jdk.jfr/share/classes/jdk/jfr/consumer/RecordingFile.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/consumer/AbstractEventStream.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/consumer/ChunkParser.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/consumer/EventDirectoryStream.java
! src/jdk.jfr/share/classes/jdk/jfr/internal/consumer/EventFileStream.java
+ src/jdk.jfr/share/classes/jdk/jfr/internal/consumer/ParserState.java

Changeset: f1fbba23
Author:    Jesper Wilhelmsson <jwilhelm at openjdk.org>
Date:      2021-12-22 16:46:43 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/f1fbba23ebdb28a32977241f8e85b60e10878cbc

Merge

! src/hotspot/cpu/x86/assembler_x86.cpp
! src/hotspot/cpu/x86/assembler_x86.hpp
! src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp
! src/hotspot/cpu/x86/c2_MacroAssembler_x86.hpp
! src/hotspot/cpu/x86/x86.ad
! test/jdk/jdk/incubator/vector/Byte512VectorTests.java
! src/hotspot/cpu/x86/assembler_x86.cpp
! src/hotspot/cpu/x86/assembler_x86.hpp
! src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp
! src/hotspot/cpu/x86/c2_MacroAssembler_x86.hpp
! src/hotspot/cpu/x86/x86.ad
! test/jdk/jdk/incubator/vector/Byte512VectorTests.java

Changeset: d64820df
Author:    Valerie Peng <valeriep at openjdk.org>
Date:      2021-12-22 19:50:51 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/d64820dfefc0bac578df43fe58d2bce8577ec94e

8209398: sun/security/pkcs11/KeyStore/SecretKeysBasic.sh failed with "PKCS11Exception: CKR_ATTRIBUTE_SENSITIVE"

Reviewed-by: hchao, weijun

! src/jdk.crypto.cryptoki/share/classes/sun/security/pkcs11/P11Key.java
! test/jdk/ProblemList.txt

Changeset: eaefb1a1
Author:    Chris Plummer <cjplummer at openjdk.org>
Date:      2021-12-22 23:02:41 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/eaefb1a1ed9edea440628e3a5c5483ebd52bfcb0

8244669: convert clhsdb "mem" command from javascript to java

Reviewed-by: sspitsyn, kevinw, poonam

! src/jdk.hotspot.agent/doc/clhsdb.html
! src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/CommandProcessor.java
! test/hotspot/jtreg/serviceability/sa/ClhsdbFindPC.java

Changeset: ad1dc9c2
Author:    Yi Yang <yyang at openjdk.org>
Date:      2021-12-23 02:14:52 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ad1dc9c2ae5463363aff20072a3f2ca4ea23acd2

8278125: Some preallocated OOMEs are missing stack trace

Co-authored-by: dongyun.tdy <dongyun.tdy at alibaba-inc.com>
Reviewed-by: dholmes, coleenp

! src/hotspot/share/memory/universe.cpp
! src/hotspot/share/memory/universe.hpp
! src/hotspot/share/utilities/exceptions.cpp
+ test/hotspot/jtreg/runtime/ErrorHandling/GenOutOfMemoryError.java

Changeset: 214f98f6
Author:    Andrew Leonard <aleonard at openjdk.org>
Date:      2021-12-23 11:01:26 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/214f98f6b07e312e6f4ded5364a94277114784e7

8278766: Enable OpenJDK build support for reproducible jars and jmods using --date

Reviewed-by: erikj

! make/CreateJmods.gmk
! make/InitSupport.gmk
! make/autoconf/basic_tools.m4
! make/autoconf/boot-jdk.m4
! make/autoconf/spec.gmk.in
! make/autoconf/util.m4
! make/common/JarArchive.gmk

Changeset: 87cc4e50
Author:    Daniel Le <greenrecyclebin at gmail.com>
Committer: Naoto Sato <naoto at openjdk.org>
Date:      2021-12-23 14:11:11 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/87cc4e5009f6b900c62a91dda1c2f98e4821a492

8276302: Locale.filterTags methods ignore actual weight when matching "*" (as if it is 1)

Reviewed-by: naoto

! src/java.base/share/classes/sun/util/locale/LocaleMatcher.java
! test/jdk/java/util/Locale/Bug7069824.java

Changeset: 558a6824
Author:    Jonathan Gibbons <jjg at openjdk.org>
Date:      2021-12-23 15:19:55 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/558a6824c6db805a2b220ab13ed95624df515538

8279115: Fix internal doc comment errors.

Reviewed-by: mli

! src/jdk.javadoc/share/classes/jdk/javadoc/internal/doclets/toolkit/ConstructorWriter.java
! src/jdk.javadoc/share/classes/jdk/javadoc/internal/doclets/toolkit/EnumConstantWriter.java
! src/jdk.javadoc/share/classes/jdk/javadoc/internal/doclets/toolkit/MethodWriter.java

Changeset: bc0466c7
Author:    Andrew Leonard <aleonard at openjdk.org>
Date:      2021-12-23 18:03:05 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/bc0466c7ca57f14b1e6285e2a39755d57c8de376

8279182: MakeZipReproducible ZipEntry timestamps not localized to UTC

Reviewed-by: erikj

! make/jdk/src/classes/build/tools/makezipreproducible/MakeZipReproducible.java

Changeset: ff2ca4f2
Author:    Vicente Romero <vromero at openjdk.org>
Date:      2021-12-23 19:12:24 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/ff2ca4f21b7bd9d5afc6c74d8d369b3a0b8a4f19

8205187: javac/javadoc should not crash if no java.lang; crash message obsolete

Reviewed-by: jjg

! src/jdk.compiler/share/classes/com/sun/tools/javac/comp/TypeEnter.java
! src/jdk.compiler/share/classes/com/sun/tools/javac/resources/compiler.properties
! test/langtools/tools/javac/diags/examples/NoJavaLang.java
! test/langtools/tools/javac/fatalErrors/NoJavaLangTest.java

Changeset: 7aff03ae
Author:    Xin Liu <xliu at openjdk.org>
Date:      2021-12-23 20:25:08 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/7aff03aee1a5cd70638d8bbafeb7765bc7beea45

8267517: async logging for stdout and stderr

Reviewed-by: dholmes, ysuenaga

! src/hotspot/share/logging/logAsyncWriter.cpp
! src/hotspot/share/logging/logAsyncWriter.hpp
! src/hotspot/share/logging/logFileOutput.cpp
! src/hotspot/share/logging/logFileOutput.hpp
! src/hotspot/share/logging/logFileStreamOutput.cpp
! src/hotspot/share/logging/logFileStreamOutput.hpp
! test/hotspot/gtest/logging/test_asynclog.cpp

Changeset: 9df200f7
Author:    Jonathan Gibbons <jjg at openjdk.org>
Date:      2021-12-23 21:15:21 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/9df200f749e6326f1d4a22cca770284f38c2de8c

8278795: Create test library and tests for langtools snippets

Reviewed-by: hannesw

+ test/langtools/jdk/javadoc/doclet/testDocletExample/TestDocletExample.java
+ test/langtools/tools/javac/api/snippets/TestJavaxToolsSnippets.java
+ test/langtools/tools/lib/snippets/SnippetUtils.java

Changeset: 2be3e7ef
Author:    Coleen Phillimore <coleenp at openjdk.org>
Date:      2021-12-22 17:19:00 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/2be3e7ef1cff1aae6faf1f4f0545d561af48d0ba

8278239: vmTestbase/nsk/jvmti/RedefineClasses/StressRedefine failed with EXCEPTION_ACCESS_VIOLATION at 0x000000000000000d

Reviewed-by: kvn, sspitsyn, eosterlund

! src/hotspot/share/code/codeCache.cpp

Changeset: 04ee9211
Author:    Stuart Marks <smarks at openjdk.org>
Date:      2021-12-22 18:56:30 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/04ee9211fcc59178b3bfdfdda5e0def9b0f29ada

8278967: rmiregistry fails to start because SecurityManager is disabled

Reviewed-by: alanb, erikj

! make/modules/java.rmi/Launcher.gmk
! test/jdk/tools/launcher/VersionCheck.java

Changeset: 9d5ae2e3
Author:    Aleksey Shipilev <shade at openjdk.org>
Date:      2021-12-22 20:17:39 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/9d5ae2e38074c3df354aeab19ebbab7d4872165a

8279076: C2: Bad AD file when matching SqrtF with UseSSE=0

Reviewed-by: kvn, sviswanathan

! src/hotspot/cpu/x86/x86.ad
+ test/hotspot/jtreg/compiler/c2/TestSqrt.java

Changeset: 730f6708
Author:    Erik Gahlin <egahlin at openjdk.org>
Date:      2021-12-23 15:03:06 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/730f67081dcda37df7fc40eda99ebd39028be15f

8268297: jdk/jfr/api/consumer/streaming/TestLatestEvent.java times out

Reviewed-by: mgronlun

! src/hotspot/share/jfr/recorder/repository/jfrChunk.cpp
! test/jdk/ProblemList.txt
! test/jdk/jdk/jfr/api/consumer/streaming/TestLatestEvent.java

Changeset: 04ad6689
Author:    Aleksey Shipilev <shade at openjdk.org>
Date:      2021-12-23 16:22:10 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/04ad668921abbd71dfbc474eed6f1760f7a541b1

8279204: [BACKOUT] JDK-8278413: C2 crash when allocating array of size too large

Reviewed-by: chagedorn, kvn

! src/hotspot/share/opto/callnode.cpp
! src/hotspot/share/opto/callnode.hpp
! src/hotspot/share/opto/cfgnode.cpp
! src/hotspot/share/opto/compile.cpp
! src/hotspot/share/opto/graphKit.cpp
! src/hotspot/share/opto/macro.cpp
! src/hotspot/share/opto/macro.hpp
! src/hotspot/share/opto/split_if.cpp
- test/hotspot/jtreg/compiler/allocation/TestFailedAllocationBadGraph.java

Changeset: a3b1c6b0
Author:    Jesper Wilhelmsson <jwilhelm at openjdk.org>
Date:      2021-12-23 21:17:50 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/a3b1c6b03600da21b00a1f37ea4712096d636b14

Merge

! src/hotspot/cpu/x86/x86.ad
! src/hotspot/share/opto/compile.cpp
! test/jdk/ProblemList.txt
! src/hotspot/cpu/x86/x86.ad
! src/hotspot/share/opto/compile.cpp
! test/jdk/ProblemList.txt

Changeset: 4669bcd8
Author:    Vicente Romero <vromero at openjdk.org>
Date:      2021-12-23 21:26:31 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/4669bcd877c89b63739abd8087ea934c7126fb3f

8279244: test accompaning fix for JDK-8205187 is failing in Windows

Reviewed-by: dcubed, mikael

! test/langtools/tools/javac/fatalErrors/NoJavaLangTest.java

Changeset: 9d99a377
Author:    Daniel Jelinski <djelinski1 at gmail.com>
Committer: Anthony Scarpino <ascarpino at openjdk.org>
Date:      2021-12-24 00:01:46 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/9d99a377bfb6ffa890db049aee575e97914fc2a1

8277881: Missing SessionID in TLS1.3 resumption in compatibility mode

Reviewed-by: ascarpino

! src/java.base/share/classes/sun/security/ssl/ClientHello.java
! src/java.base/share/classes/sun/security/ssl/SSLConfiguration.java
! test/jdk/javax/net/ssl/SSLSession/ResumeTLS13withSNI.java

Changeset: 22c15dda
Author:    Xin Liu <xliu at openjdk.org>
Date:      2021-12-24 00:57:03 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/22c15ddae5ef7431f677edf4df9a403613716def

8279189: Inaccurate comment about class VMThread

Reviewed-by: dholmes, kbarrett

! src/hotspot/share/runtime/vmThread.hpp

Changeset: d52392c1
Author:    Jonathan Gibbons <jjg at openjdk.org>
Date:      2021-12-24 01:48:13 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/d52392c15e47dbfbba7eda0739ff8e6f29613b53

8276892: Provide a way to emulate exceptional situations in FileManager when using JavadocTester

Reviewed-by: prappo

! src/jdk.javadoc/share/classes/jdk/javadoc/internal/doclets/toolkit/resources/doclets.properties
! src/jdk.javadoc/share/classes/jdk/javadoc/internal/tool/Main.java
! src/jdk.javadoc/share/classes/jdk/javadoc/internal/tool/Start.java
! src/jdk.javadoc/share/classes/jdk/javadoc/internal/tool/resources/javadoc.properties
! test/langtools/jdk/javadoc/lib/javadoc/tester/JavadocTester.java
+ test/langtools/jdk/javadoc/lib/javadoc/tester/TestJavaFileManagerBuilder.java
+ test/langtools/jdk/javadoc/testTFMBuilder/TestTFMBuilder.java

Changeset: 1fcf5647
Author:    Fei Yang <felix.yang at huawei.com>
Date:      2021-12-23 21:04:39 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/1fcf5647842e83eb05d68181b58155210642f0bf

Merge branch 'master' into riscv-port

! src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
! src/hotspot/cpu/riscv/vm_version_riscv.cpp
! src/hotspot/cpu/riscv/vm_version_riscv.hpp
+ src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
+ src/hotspot/cpu/riscv/vm_version_riscv.cpp
+ src/hotspot/cpu/riscv/vm_version_riscv.hpp


From fyang at openjdk.java.net  Fri Dec 24 07:18:49 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Fri, 24 Dec 2021 07:18:49 GMT
Subject: [riscv-port] RFR: 8278994: riscv: RVC: basic instruction set
In-Reply-To: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
References: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
Message-ID: <3JEP2Sb1Q0eNeJDLU7e_ht4pFKTb11YEiOnt1Zo0hHs=.a47a8f27-585d-440a-8998-50da136d1c92@github.com>

On Mon, 20 Dec 2021 08:10:10 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
> 
> This patch includes the basic definition of the RVC instruction set and some cleanups. Tested a simple `test/hotspot/jtreg/compiler/` folder on qemu.
> 
> Thanks,
> Xiaolin

Changes requested by fyang (Lead).

src/hotspot/cpu/riscv/assembler_riscv_c.hpp line 27:

> 25: 
> 26: #ifndef CPU_RISCV_ASSEMBLER_RISCV_CEXT_HPP
> 27: #define CPU_RISCV_ASSEMBLER_RISCV_CEXT_HPP

This should corresponds to the real file name

src/hotspot/cpu/riscv/assembler_riscv_c.hpp line 30:

> 28: 
> 29: private:
> 30:   bool _in_compressible_region;

So where will this variable be used then?

src/hotspot/cpu/riscv/assembler_riscv_c.hpp line 36:

> 34: public:
> 35: 
> 36:   // C-Ext: If an instruction is compressible, then

I would suggest we change "C-Ext" into something like "RVC".

src/hotspot/cpu/riscv/assembler_riscv_c.hpp line 67:

> 65: 
> 66:   // C-Ext: extract a 16-bit instruction.
> 67:   static inline uint16_t c_extract(uint16_t val, unsigned msb, unsigned lsb) {

We definitely need test coverage for those newly added assember functions for this PR.

src/hotspot/cpu/riscv/assembler_riscv_c.hpp line 571:

> 569: 
> 570: // C-Ext: an uncompressible region
> 571: class UncompressibleRegion : public AbstractCompressibleRegion {

It looks strange that UncompressibleRegion extends the abstract 'compressible' region here.

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 1321:

> 1319: #ifdef ASSERT
> 1320:     tty->print_cr("pd_patch_instruction_size: instruction 0x%x at " INTPTR_FORMAT " could not be patched!\n", *(unsigned*)branch, p2i(branch));
> 1321:     Disassembler::decode(branch - 10, branch + 10);

How is this change tested?

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/34

From xlinzheng at openjdk.java.net  Fri Dec 24 07:55:24 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Fri, 24 Dec 2021 07:55:24 GMT
Subject: [riscv-port] RFR: 8278994: riscv: RVC support [v2]
In-Reply-To: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
References: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
Message-ID: <ukxoiHOhnXD73_SN0lSZ4PpLUuvlvhx-LYtrKxJpVdk=.886cb258-0b9b-4060-83e0-0d0c99c318d9@github.com>

> Hi team,
> 
> This patch includes the basic definition of the RVC instruction set and some cleanups. Tested a simple `test/hotspot/jtreg/compiler/` folder on qemu.
> 
> Thanks,
> Xiaolin

Xiaolin Zheng has updated the pull request incrementally with three additional commits since the last revision:

 - Cover most RVC instructions by using CompressibleRegion to cover minimal functions in C2
 - Revise as proposed comments, including
   - Fix macros in assembler_riscv_c.hpp
   - Remove UncompressibleRegion
   - Modify comments
   - Change names: C-Ext to RVC
 - Enable RVC instructions (based on the basic patch)

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/34/files
  - new: https://git.openjdk.java.net/riscv-port/pull/34/files/41ec7bd1..dbc763ed

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=34&range=01
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=34&range=00-01

  Stats: 622 lines in 13 files changed: 479 ins; 32 del; 111 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/34.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/34/head:pull/34

PR: https://git.openjdk.java.net/riscv-port/pull/34

From xlinzheng at openjdk.java.net  Fri Dec 24 08:15:46 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Fri, 24 Dec 2021 08:15:46 GMT
Subject: [riscv-port] RFR: 8278994: riscv: RVC support [v2]
In-Reply-To: <ukxoiHOhnXD73_SN0lSZ4PpLUuvlvhx-LYtrKxJpVdk=.886cb258-0b9b-4060-83e0-0d0c99c318d9@github.com>
References: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
 <ukxoiHOhnXD73_SN0lSZ4PpLUuvlvhx-LYtrKxJpVdk=.886cb258-0b9b-4060-83e0-0d0c99c318d9@github.com>
Message-ID: <eaYhK7UoEyPcxUdYZZ6Isit_-Pgek79XHjDLqygrYZ4=.955f3025-39c2-4ece-97ba-195ebb80fde3@github.com>

On Fri, 24 Dec 2021 07:55:24 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> Hi team,
>> 
>> This patch includes the basic definition of the RVC instruction set and some cleanups. Tested a simple `test/hotspot/jtreg/compiler/` folder on qemu.
>> 
>> Thanks,
>> Xiaolin
>
> Xiaolin Zheng has updated the pull request incrementally with three additional commits since the last revision:
> 
>  - Cover most RVC instructions by using CompressibleRegion to cover minimal functions in C2
>  - Revise as proposed comments, including
>    - Fix macros in assembler_riscv_c.hpp
>    - Remove UncompressibleRegion
>    - Modify comments
>    - Change names: C-Ext to RVC
>  - Enable RVC instructions (based on the basic patch)

Thanks for your reviews, Felix. In the morning Yadong discussed with me your review comments, so I have pushed additional patches to ensure nearly all functions I defined have been properly 'use'd. I think that might increase the burden to review this patch because of the new changes, and I feel quite sorry for that.

Now excluding `c.beqz`, `c.bnez` and `c.j`, which need to be supported in `MachBranchNode`s afterward by Wei Kuai, all RVC instructions have been covered in usage by adding `CompressibleRegion`s in the ad file. Also, I revised the comments in the code based on your suggestions and hope they look good.

This may need another period to review so no rush. Also, due to [Wei Kuai's code](https://github.com/openjdk/riscv-port/blob/dbc763edfbee277125283fdd0cf98f46d42f5e12/src/hotspot/cpu/riscv/riscv.ad#L1193-L1219) is added into this patch now, I assume I should add him as a co-author of this patch.

Hmm. Hope this time it could succeed.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/34

From xlinzheng at openjdk.java.net  Fri Dec 24 08:21:45 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Fri, 24 Dec 2021 08:21:45 GMT
Subject: [riscv-port] RFR: 8278994: riscv: RVC support [v2]
In-Reply-To: <ukxoiHOhnXD73_SN0lSZ4PpLUuvlvhx-LYtrKxJpVdk=.886cb258-0b9b-4060-83e0-0d0c99c318d9@github.com>
References: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
 <ukxoiHOhnXD73_SN0lSZ4PpLUuvlvhx-LYtrKxJpVdk=.886cb258-0b9b-4060-83e0-0d0c99c318d9@github.com>
Message-ID: <1nU3I0QvRsR03cdkEkJNrgsXAv9pxuQNg5_phspmtbo=.5c040478-b7e0-45f0-b95b-91b6dfb2590a@github.com>

On Fri, 24 Dec 2021 07:55:24 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> Hi team,
>> 
>> This patch includes the basic definition of the RVC instruction set and some cleanups. Tested a simple `test/hotspot/jtreg/compiler/` folder on qemu.
>> 
>> Thanks,
>> Xiaolin
>
> Xiaolin Zheng has updated the pull request incrementally with three additional commits since the last revision:
> 
>  - Cover most RVC instructions by using CompressibleRegion to cover minimal functions in C2
>  - Revise as proposed comments, including
>    - Fix macros in assembler_riscv_c.hpp
>    - Remove UncompressibleRegion
>    - Modify comments
>    - Change names: C-Ext to RVC
>  - Enable RVC instructions (based on the basic patch)

-- Quite feel sorry for the disturbance :-(

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/34

From xlinzheng at openjdk.java.net  Fri Dec 24 08:25:50 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Fri, 24 Dec 2021 08:25:50 GMT
Subject: [riscv-port] RFR: 8278994: riscv: RVC support [v2]
In-Reply-To: <3JEP2Sb1Q0eNeJDLU7e_ht4pFKTb11YEiOnt1Zo0hHs=.a47a8f27-585d-440a-8998-50da136d1c92@github.com>
References: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
 <3JEP2Sb1Q0eNeJDLU7e_ht4pFKTb11YEiOnt1Zo0hHs=.a47a8f27-585d-440a-8998-50da136d1c92@github.com>
Message-ID: <rSw-ri2M0aBUrueAzpT1y1q_iIy3nhexBYK01NnjY3c=.e7497ced-7034-406e-b064-cb71d66dc966@github.com>

On Fri, 24 Dec 2021 07:13:09 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Xiaolin Zheng has updated the pull request incrementally with three additional commits since the last revision:
>> 
>>  - Cover most RVC instructions by using CompressibleRegion to cover minimal functions in C2
>>  - Revise as proposed comments, including
>>    - Fix macros in assembler_riscv_c.hpp
>>    - Remove UncompressibleRegion
>>    - Modify comments
>>    - Change names: C-Ext to RVC
>>  - Enable RVC instructions (based on the basic patch)
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 1321:
> 
>> 1319: #ifdef ASSERT
>> 1320:     tty->print_cr("pd_patch_instruction_size: instruction 0x%x at " INTPTR_FORMAT " could not be patched!\n", *(unsigned*)branch, p2i(branch));
>> 1321:     Disassembler::decode(branch - 10, branch + 10);
> 
> How is this change tested?

This is a pretty print and I deliberately violated one `movptr` under relocation to test it. If it looks not good I could remove that.

Other comments are fixed in the new patches.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/34

From xlinzheng at openjdk.java.net  Fri Dec 24 09:57:50 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Fri, 24 Dec 2021 09:57:50 GMT
Subject: [riscv-port] RFR: 8278994: riscv: RVC support [v2]
In-Reply-To: <3JEP2Sb1Q0eNeJDLU7e_ht4pFKTb11YEiOnt1Zo0hHs=.a47a8f27-585d-440a-8998-50da136d1c92@github.com>
References: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
 <3JEP2Sb1Q0eNeJDLU7e_ht4pFKTb11YEiOnt1Zo0hHs=.a47a8f27-585d-440a-8998-50da136d1c92@github.com>
Message-ID: <bIW6fLflBd5s8P68FvuggBTCkINr8n2w9GbpJyZthC4=.12635b40-ed4c-405b-a19c-0d3b7fb65aad@github.com>

On Fri, 24 Dec 2021 07:08:31 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Xiaolin Zheng has updated the pull request incrementally with three additional commits since the last revision:
>> 
>>  - Cover most RVC instructions by using CompressibleRegion to cover minimal functions in C2
>>  - Revise as proposed comments, including
>>    - Fix macros in assembler_riscv_c.hpp
>>    - Remove UncompressibleRegion
>>    - Modify comments
>>    - Change names: C-Ext to RVC
>>  - Enable RVC instructions (based on the basic patch)
>
> src/hotspot/cpu/riscv/assembler_riscv_c.hpp line 30:
> 
>> 28: 
>> 29: private:
>> 30:   bool _in_compressible_region;
> 
> So where will this variable be used then?

Sorry I missed this comment. This variable `_in_compressible_region` is used in `CompressibleRegion cr(&_masm)`. During [RTTI](https://github.com/openjdk/riscv-port/blob/dbc763edfbee277125283fdd0cf98f46d42f5e12/src/hotspot/cpu/riscv/assembler_riscv_c.hpp#L873-L877) this variable is set, and when emitting instructions inside the region, instructions inside the region will be considered qualified as safe to be emitted as RVC instructions -- please see the [macros](https://github.com/openjdk/riscv-port/blob/dbc763edfbee277125283fdd0cf98f46d42f5e12/src/hotspot/cpu/riscv/assembler_riscv_c.hpp#L553-L576) and [an example usage](https://github.com/openjdk/riscv-port/blob/dbc763edfbee277125283fdd0cf98f46d42f5e12/src/hotspot/cpu/riscv/assembler_riscv_c.hpp#L601-L606).

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/34

From fjiang at openjdk.java.net  Sat Dec 25 05:00:44 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Sat, 25 Dec 2021 05:00:44 GMT
Subject: [riscv-port] RFR: 8279213: riscv: RVB: Add zero/sign extend
 instructions [v2]
In-Reply-To: <Q0T8I10auByw_sZSPSjRl3QGkzpI3rom4oMNMLtpKVo=.abeffae0-72fb-40a4-a116-ea69c4a997f6@github.com>
References: <LhacNhG7XNX__Rpy50FFj9t76i6IMq-C1UiWgrzNAVY=.5043e857-bf32-4aae-862e-02d800b0e805@github.com>
 <9O5_EQedXJ5tabiy-5iGzusDrhRBymZOtHxHrBk4PYI=.1f54d384-754e-431b-818a-6aea7fb117d8@github.com>
 <Q0T8I10auByw_sZSPSjRl3QGkzpI3rom4oMNMLtpKVo=.abeffae0-72fb-40a4-a116-ea69c4a997f6@github.com>
Message-ID: <uGIPXAwoQEg4b65xI3lOFi3v7h1YgZA-pBQXEEZXaFQ=.1db99ca4-7df3-4ade-beaa-40c8664b31a1@github.com>

On Sat, 25 Dec 2021 03:20:29 GMT, Fei Yang <fyang at openjdk.org> wrote:

> Looks good. Thanks for refactoring the existing zero/sign extension code. Also passed some extra load testing on the unmatched board (where RVB extension is not available).

Thanks for the reviews and tests, Felix. After pushing another commit to add `zext.b`, hotspot and jdk tier1 tests are still passed on QEMU when RVB is enabled.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/37

From duke at openjdk.java.net  Sat Dec 25 09:40:39 2021
From: duke at openjdk.java.net (duke)
Date: Sat, 25 Dec 2021 09:40:39 GMT
Subject: git: openjdk/riscv-port: riscv-port: 2 new changesets
Message-ID: <b64f5460-2071-4519-aebb-dbe252d563b2@openjdk.java.net>

Changeset: 70c6df6b
Author:    Andrey Turbanov <turbanoff at gmail.com>
Committer: Sergey Bylokhov <serb at openjdk.org>
Date:      2021-12-24 02:02:39 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/70c6df6be431fe11c5441986ed04040f9ec3b750

8274893: Update java.desktop classes to use try-with-resources

Reviewed-by: serb

! src/java.desktop/share/classes/com/sun/imageio/plugins/png/PNGImageReader.java
! src/java.desktop/share/classes/com/sun/java/swing/plaf/gtk/Metacity.java
! src/java.desktop/share/classes/com/sun/media/sound/AudioFileSoundbankReader.java
! src/java.desktop/share/classes/com/sun/media/sound/DLSSoundbank.java
! src/java.desktop/share/classes/com/sun/media/sound/JARSoundbankReader.java
! src/java.desktop/share/classes/com/sun/media/sound/ModelByteBuffer.java
! src/java.desktop/share/classes/com/sun/media/sound/ModelByteBufferWavetable.java
! src/java.desktop/share/classes/com/sun/media/sound/SF2Soundbank.java
! src/java.desktop/share/classes/com/sun/media/sound/SoftSynthesizer.java
! src/java.desktop/share/classes/com/sun/media/sound/StandardMidiFileReader.java
! src/java.desktop/share/classes/com/sun/media/sound/StandardMidiFileWriter.java
! src/java.desktop/share/classes/java/awt/Font.java
! src/java.desktop/share/classes/java/awt/Toolkit.java
! src/java.desktop/share/classes/java/beans/Beans.java
! src/java.desktop/share/classes/javax/imageio/ImageIO.java
! src/java.desktop/share/classes/javax/swing/JEditorPane.java
! src/java.desktop/share/classes/javax/swing/UIManager.java
! src/java.desktop/share/classes/javax/swing/text/html/HTMLEditorKit.java
! src/java.desktop/share/classes/javax/swing/text/html/StyleSheet.java
! src/java.desktop/share/classes/sun/awt/DebugSettings.java
! src/java.desktop/share/classes/sun/awt/FontConfiguration.java
! src/java.desktop/share/classes/sun/print/PSPrinterJob.java
! src/java.desktop/unix/classes/sun/font/FcFontConfiguration.java
! src/java.desktop/unix/classes/sun/font/MFontConfiguration.java

Changeset: 8e0df0d2
Author:    Fei Yang <felix.yang at huawei.com>
Date:      2021-12-25 04:38:52 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/8e0df0d2186bb446aa96ba89c60124d657d16d1e

Merge branch 'master' into riscv-port



From xlinzheng at openjdk.java.net  Mon Dec 27 02:56:59 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Mon, 27 Dec 2021 02:56:59 GMT
Subject: [riscv-port] RFR: 8278994: riscv: RVC support [v3]
In-Reply-To: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
References: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
Message-ID: <7-Glwkwqzp0USUo1Y4BXNmYwi72MPWzaxlVvumh427Q=.900b54a8-9dc8-4abb-b923-25e88b942c05@github.com>

> Hi team,
> 
> This patch includes the basic definition of the RVC instruction set and some cleanups. Tested a simple `test/hotspot/jtreg/compiler/` folder on qemu.
> 
> Using `<JAVA_HOME>/bin/java -XX:+UnlockExperimentalVMOptions -XX:+UseRVC -XX:+UnlockDiagnosticVMOptions -XX:+PrintAssembly -XX:PrintAssemblyOptions=no-aliases,numeric -XX:+PrintStubCode -XX:-TieredCompilation` could show RVC instructions.
> 
> Thanks,
> Xiaolin

Xiaolin Zheng has updated the pull request with a new target base due to a merge or a rebase. The pull request now contains four commits:

 - Cover most RVC instructions by using CompressibleRegion to cover minimal functions in C2
 - Revise as proposed comments, including
   - Fix macros in assembler_riscv_c.hpp
   - Remove UncompressibleRegion
   - Modify comments
   - Change names: C-Ext to RVC
 - Enable RVC instructions (based on the basic patch)
 - RVC: basic instruction set

-------------

Changes: https://git.openjdk.java.net/riscv-port/pull/34/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=34&range=02
  Stats: 1177 lines in 15 files changed: 1061 ins; 10 del; 106 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/34.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/34/head:pull/34

PR: https://git.openjdk.java.net/riscv-port/pull/34

From xlinzheng at openjdk.java.net  Mon Dec 27 02:57:00 2021
From: xlinzheng at openjdk.java.net (Xiaolin Zheng)
Date: Mon, 27 Dec 2021 02:57:00 GMT
Subject: [riscv-port] RFR: 8278994: riscv: RVC support [v2]
In-Reply-To: <ukxoiHOhnXD73_SN0lSZ4PpLUuvlvhx-LYtrKxJpVdk=.886cb258-0b9b-4060-83e0-0d0c99c318d9@github.com>
References: <VOkGRMcwt1FlHZMlPbvcSYWZF-i_H9iV4DjD-CRlWuY=.d44f724f-93ff-48b1-9828-39dbb04e6e9c@github.com>
 <ukxoiHOhnXD73_SN0lSZ4PpLUuvlvhx-LYtrKxJpVdk=.886cb258-0b9b-4060-83e0-0d0c99c318d9@github.com>
Message-ID: <HnuDcjaRPev5c9zO7tYq7ATp4O-lndhyty90XUiIpxg=.9cfacc5c-2209-44b4-a527-66b5ac8d46bc@github.com>

On Fri, 24 Dec 2021 07:55:24 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> Hi team,
>> 
>> This patch includes the basic definition of the RVC instruction set and some cleanups. Tested a simple `test/hotspot/jtreg/compiler/` folder on qemu.
>> 
>> Using `<JAVA_HOME>/bin/java -XX:+UnlockExperimentalVMOptions -XX:+UseRVC -XX:+UnlockDiagnosticVMOptions -XX:+PrintAssembly -XX:PrintAssemblyOptions=no-aliases,numeric -XX:+PrintStubCode -XX:-TieredCompilation` could show RVC instructions.
>> 
>> Thanks,
>> Xiaolin
>
> Xiaolin Zheng has updated the pull request incrementally with three additional commits since the last revision:
> 
>  - Cover most RVC instructions by using CompressibleRegion to cover minimal functions in C2
>  - Revise as proposed comments, including
>    - Fix macros in assembler_riscv_c.hpp
>    - Remove UncompressibleRegion
>    - Modify comments
>    - Change names: C-Ext to RVC
>  - Enable RVC instructions (based on the basic patch)

Rebased and fixed conflicts with RVB(#37)'s initial load. Tested build and a simple spring-boot application with/without RVC.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/34

From duke at openjdk.java.net  Mon Dec 27 06:39:18 2021
From: duke at openjdk.java.net (duke)
Date: Mon, 27 Dec 2021 06:39:18 GMT
Subject: git: openjdk/riscv-port: riscv-port: 6 new changesets
Message-ID: <7b52c9b5-631d-4661-9541-18ea3170f37d@openjdk.java.net>

Changeset: 7fea1032
Author:    Sergey Bylokhov <serb at openjdk.org>
Date:      2021-12-26 22:10:54 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/7fea10327ed27fcf8eae474ca5b15c3b4bafff2a

8279134: Fix Amazon copyright in various files

Reviewed-by: xliu, phh

! src/hotspot/cpu/aarch64/spin_wait_aarch64.hpp
! src/hotspot/share/gc/g1/g1OldGenAllocationTracker.cpp
! src/hotspot/share/gc/g1/g1OldGenAllocationTracker.hpp
! test/hotspot/jtreg/compiler/onSpinWait/TestOnSpinWaitAArch64.java
! test/hotspot/jtreg/compiler/onSpinWait/TestOnSpinWaitAArch64DefaultFlags.java
! test/hotspot/jtreg/compiler/onSpinWait/TestOnSpinWaitNoneAArch64.java
! test/hotspot/jtreg/runtime/Thread/TestSpinPause.java
! test/hotspot/jtreg/serviceability/dcmd/compiler/CodeHeapAnalyticsMethodNames.java
! test/jdk/java/io/File/LastModifiedTest.java
! test/jdk/java/security/KeyFactory/KeyFactoryGetKeySpecForInvalidSpec.java
! test/jdk/sun/security/pkcs11/rsa/TestP11KeyFactoryGetRSAKeySpec.java
! test/jdk/sun/security/ssl/SSLSocketImpl/SSLSocketShouldThrowSocketException.java
! test/micro/org/openjdk/bench/java/lang/ThreadOnSpinWait.java
! test/micro/org/openjdk/bench/java/lang/ThreadOnSpinWaitProducerConsumer.java

Changeset: 6588bedc
Author:    Eric Liu <eliu at openjdk.org>
Committer: Vladimir Kozlov <kvn at openjdk.org>
Date:      2021-12-24 03:10:41 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/6588bedc19ab42cec9e5bb6f13be14fb4dc5a655

8278889: AArch64: [vectorapi] VectorMaskLoadStoreTest.testMaskCast() test fail

Reviewed-by: njian, kvn

! src/hotspot/cpu/aarch64/aarch64_sve.ad
! src/hotspot/cpu/aarch64/aarch64_sve_ad.m4
! src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp
! src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp
! test/hotspot/gtest/aarch64/aarch64-asmtest.py
! test/hotspot/gtest/aarch64/asmtest.out.h
! test/jdk/jdk/incubator/vector/Byte128VectorTests.java
! test/jdk/jdk/incubator/vector/Byte256VectorTests.java
! test/jdk/jdk/incubator/vector/Byte512VectorTests.java
! test/jdk/jdk/incubator/vector/Byte64VectorTests.java
! test/jdk/jdk/incubator/vector/ByteMaxVectorTests.java
! test/jdk/jdk/incubator/vector/Double128VectorTests.java
! test/jdk/jdk/incubator/vector/Double256VectorTests.java
! test/jdk/jdk/incubator/vector/Double512VectorTests.java
! test/jdk/jdk/incubator/vector/Double64VectorTests.java
! test/jdk/jdk/incubator/vector/DoubleMaxVectorTests.java
! test/jdk/jdk/incubator/vector/Float128VectorTests.java
! test/jdk/jdk/incubator/vector/Float256VectorTests.java
! test/jdk/jdk/incubator/vector/Float512VectorTests.java
! test/jdk/jdk/incubator/vector/Float64VectorTests.java
! test/jdk/jdk/incubator/vector/FloatMaxVectorTests.java
! test/jdk/jdk/incubator/vector/Int128VectorTests.java
! test/jdk/jdk/incubator/vector/Int256VectorTests.java
! test/jdk/jdk/incubator/vector/Int512VectorTests.java
! test/jdk/jdk/incubator/vector/Int64VectorTests.java
! test/jdk/jdk/incubator/vector/IntMaxVectorTests.java
! test/jdk/jdk/incubator/vector/Long128VectorTests.java
! test/jdk/jdk/incubator/vector/Long256VectorTests.java
! test/jdk/jdk/incubator/vector/Long512VectorTests.java
! test/jdk/jdk/incubator/vector/Long64VectorTests.java
! test/jdk/jdk/incubator/vector/LongMaxVectorTests.java
! test/jdk/jdk/incubator/vector/Short128VectorTests.java
! test/jdk/jdk/incubator/vector/Short256VectorTests.java
! test/jdk/jdk/incubator/vector/Short512VectorTests.java
! test/jdk/jdk/incubator/vector/Short64VectorTests.java
! test/jdk/jdk/incubator/vector/ShortMaxVectorTests.java
! test/jdk/jdk/incubator/vector/templates/Unit-Miscellaneous.template

Changeset: 2945b786
Author:    Vladimir Kozlov <kvn at openjdk.org>
Date:      2021-12-24 22:32:16 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/2945b786ba6b60cc33153bb1d40ac7a0918dadbe

8279195: Document the -XX:+NeverActAsServerClassMachine flag

Reviewed-by: dholmes

! src/java.base/share/man/java.1

Changeset: 54b800d5
Author:    Igor Veresov <iveresov at openjdk.org>
Date:      2021-12-25 05:38:12 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/54b800d56d6bc86676722ad96e87b8344606bcb7

8271202: C1: assert(false) failed: live_in set of first block must be empty

Co-authored-by: Martin Doerr <mdoerr at openjdk.org>
Reviewed-by: vlivanov, kvn

! src/hotspot/share/c1/c1_LIRGenerator.cpp
+ test/hotspot/jtreg/compiler/c1/Test8271202.java

Changeset: 4f607f2a
Author:    Jesper Wilhelmsson <jwilhelm at openjdk.org>
Date:      2021-12-27 01:22:11 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/4f607f2adac3798c16a62e902ba9ce0df3ab1add

Merge

! src/java.base/share/man/java.1
! test/hotspot/gtest/aarch64/aarch64-asmtest.py
! test/hotspot/gtest/aarch64/asmtest.out.h
! test/jdk/jdk/incubator/vector/Byte128VectorTests.java
! test/jdk/jdk/incubator/vector/Byte256VectorTests.java
! test/jdk/jdk/incubator/vector/Byte512VectorTests.java
! test/jdk/jdk/incubator/vector/Byte64VectorTests.java
! test/jdk/jdk/incubator/vector/Double128VectorTests.java
! test/jdk/jdk/incubator/vector/Double256VectorTests.java
! test/jdk/jdk/incubator/vector/Double512VectorTests.java
! test/jdk/jdk/incubator/vector/Double64VectorTests.java
! test/jdk/jdk/incubator/vector/Float128VectorTests.java
! test/jdk/jdk/incubator/vector/Float256VectorTests.java
! test/jdk/jdk/incubator/vector/Float512VectorTests.java
! test/jdk/jdk/incubator/vector/Float64VectorTests.java
! test/jdk/jdk/incubator/vector/Int128VectorTests.java
! test/jdk/jdk/incubator/vector/Int256VectorTests.java
! test/jdk/jdk/incubator/vector/Int512VectorTests.java
! test/jdk/jdk/incubator/vector/Int64VectorTests.java
! test/jdk/jdk/incubator/vector/Long128VectorTests.java
! test/jdk/jdk/incubator/vector/Long256VectorTests.java
! test/jdk/jdk/incubator/vector/Long512VectorTests.java
! test/jdk/jdk/incubator/vector/Long64VectorTests.java
! test/jdk/jdk/incubator/vector/Short128VectorTests.java
! test/jdk/jdk/incubator/vector/Short256VectorTests.java
! test/jdk/jdk/incubator/vector/Short512VectorTests.java
! test/jdk/jdk/incubator/vector/Short64VectorTests.java
! test/jdk/jdk/incubator/vector/templates/Unit-Miscellaneous.template
! src/java.base/share/man/java.1
! test/hotspot/gtest/aarch64/aarch64-asmtest.py
! test/hotspot/gtest/aarch64/asmtest.out.h
! test/jdk/jdk/incubator/vector/Byte128VectorTests.java
! test/jdk/jdk/incubator/vector/Byte256VectorTests.java
! test/jdk/jdk/incubator/vector/Byte512VectorTests.java
! test/jdk/jdk/incubator/vector/Byte64VectorTests.java
! test/jdk/jdk/incubator/vector/Double128VectorTests.java
! test/jdk/jdk/incubator/vector/Double256VectorTests.java
! test/jdk/jdk/incubator/vector/Double512VectorTests.java
! test/jdk/jdk/incubator/vector/Double64VectorTests.java
! test/jdk/jdk/incubator/vector/Float128VectorTests.java
! test/jdk/jdk/incubator/vector/Float256VectorTests.java
! test/jdk/jdk/incubator/vector/Float512VectorTests.java
! test/jdk/jdk/incubator/vector/Float64VectorTests.java
! test/jdk/jdk/incubator/vector/Int128VectorTests.java
! test/jdk/jdk/incubator/vector/Int256VectorTests.java
! test/jdk/jdk/incubator/vector/Int512VectorTests.java
! test/jdk/jdk/incubator/vector/Int64VectorTests.java
! test/jdk/jdk/incubator/vector/Long128VectorTests.java
! test/jdk/jdk/incubator/vector/Long256VectorTests.java
! test/jdk/jdk/incubator/vector/Long512VectorTests.java
! test/jdk/jdk/incubator/vector/Long64VectorTests.java
! test/jdk/jdk/incubator/vector/Short128VectorTests.java
! test/jdk/jdk/incubator/vector/Short256VectorTests.java
! test/jdk/jdk/incubator/vector/Short512VectorTests.java
! test/jdk/jdk/incubator/vector/Short64VectorTests.java
! test/jdk/jdk/incubator/vector/templates/Unit-Miscellaneous.template

Changeset: 273291e2
Author:    Fei Yang <felix.yang at huawei.com>
Date:      2021-12-27 01:36:54 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/273291e2fe8210954ff626d99efa31d17b2ac33c

Merge branch 'master' into riscv-port



From felix.yang at huawei.com  Mon Dec 27 07:00:57 2021
From: felix.yang at huawei.com (Yangfei (Felix))
Date: Mon, 27 Dec 2021 07:00:57 +0000
Subject: Result: New RISC-V Port Committer: Yadong Wang
Message-ID: <dfe6956b643e4d0097695bb8ab73618b@huawei.com>

Voting for Yadong Wang [1] is now closed.

Yes: 3
Veto: 0
Abstain: 0

According to the Bylaws definition of Lazy Consensus, this is
sufficient to approve the nomination.

Felix

[1] https://mail.openjdk.java.net/pipermail/riscv-port-dev/2021-December/000143.html

From fjiang at openjdk.java.net  Mon Dec 27 08:31:11 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Mon, 27 Dec 2021 08:31:11 GMT
Subject: [riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and
 squareToLen
Message-ID: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>

On behalf of Taiping Guo (guotaiping1 at huawei.com)

BigInteger intrinsic: MultiplyToLen and SquareToLen intrinsic are missed in current vm. They should be implemented.
The JMH tests show that the MultiplyToLen intrinsic improve the performance by up to 2x ~ 3x and the SquareToLen intrinsic improve the performance by up to 1.8x ~ 2x when the length of BigInteger changed from 1 to 5000, compared with that of C2.

JMH tests and results on D1 and Unmatched list as follows:
[MyBenchmark.txt](https://github.com/openjdk/riscv-port/files/7779255/MyBenchmark.txt)

[squareToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779247/squareToLen_unmatched.txt)
[squareToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779248/squareToLen_d1.txt)
[multiplyToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779249/multiplyToLen_unmatched.txt)
[multiplyToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779250/multiplyToLen_d1.txt)

-------------

Commit messages:
 - 8279292: riscv: Intrinsify multiplyToLen and squareToLen

Changes: https://git.openjdk.java.net/riscv-port/pull/38/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=38&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8279292
  Stats: 589 lines in 4 files changed: 589 ins; 0 del; 0 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/38.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/38/head:pull/38

PR: https://git.openjdk.java.net/riscv-port/pull/38

From fyang at openjdk.java.net  Mon Dec 27 11:39:43 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Mon, 27 Dec 2021 11:39:43 GMT
Subject: [riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and
 squareToLen
In-Reply-To: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
References: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
Message-ID: <weqO_V5J5c75gV7XDUCXprxZo5aFmhznTxWfEMPZOKQ=.e9b11c78-d897-44a0-94d6-573424414d8c@github.com>

On Mon, 27 Dec 2021 08:25:22 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> BigInteger intrinsic: MultiplyToLen and SquareToLen intrinsic are missed in current vm. They should be implemented.
> The JMH tests show that the MultiplyToLen intrinsic improve the performance by up to 2x ~ 3x and the SquareToLen intrinsic improve the performance by up to 1.8x ~ 2x when the length of BigInteger changed from 1 to 5000, compared with that of C2.
> 
> Full jtreg tests on qemu and hotspot/jdk tier1 test on Unmathced are passed without new failures.
> 
> JMH tests and results on D1 and Unmatched list as follows:
> [MyBenchmark.txt](https://github.com/openjdk/riscv-port/files/7779255/MyBenchmark.txt)
> 
> [squareToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779247/squareToLen_unmatched.txt)
> [squareToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779248/squareToLen_d1.txt)
> [multiplyToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779249/multiplyToLen_unmatched.txt)
> [multiplyToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779250/multiplyToLen_d1.txt)

Changes requested by fyang (Lead).

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3249:

> 3247: 
> 3248: /**
> 3249:  * Multiply 128 bit by 128. Unrolled inner loop.

Should be: "Multiply 128 bit by 128 bit. Unrolled inner loop."

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3381:

> 3379: 
> 3380: /**
> 3381:  * Code for BigInteger::multiplyToLen() instrinsic.

There is a typo here. Should be: ""Code for BigInteger::multiplyToLen() intrinsic."

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3417:

> 3415:   mv(carry, zr); // carry = 0;
> 3416: 
> 3417:   Label L_multiply_64_or_128, L_done;

Suggestion: rename L_multiply_64_or_128 into L_multiply_64_x_64_loop

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3424:

> 3422:   const Register jdx = tmp1;
> 3423: 
> 3424:   // if x and y are both 8 bytes aligend.

There is a typo here. Maybe "// Check if x and y are both 8-byte aligned."

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/38

From fjiang at openjdk.java.net  Mon Dec 27 12:22:23 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Mon, 27 Dec 2021 12:22:23 GMT
Subject: [riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and
 squareToLen [v2]
In-Reply-To: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
References: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
Message-ID: <tRn5EnT0KVS9r9tPi9RPRRUoW9iy79MP8UbNE8FZze8=.d8a63675-63a0-4814-bcdd-5996e8983484@github.com>

> BigInteger intrinsic: MultiplyToLen and SquareToLen intrinsic are missed in current vm. They should be implemented.
> The JMH tests show that the MultiplyToLen intrinsic improve the performance by up to 2x ~ 3x and the SquareToLen intrinsic improve the performance by up to 1.8x ~ 2x when the length of BigInteger changed from 1 to 5000, compared with that of C2.
> 
> Full jtreg tests on qemu and hotspot/jdk tier1 test on Unmathced are passed without new failures.
> 
> JMH tests and results on D1 and Unmatched list as follows:
> [MyBenchmark.txt](https://github.com/openjdk/riscv-port/files/7779255/MyBenchmark.txt)
> 
> [squareToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779247/squareToLen_unmatched.txt)
> [squareToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779248/squareToLen_d1.txt)
> [multiplyToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779249/multiplyToLen_unmatched.txt)
> [multiplyToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779250/multiplyToLen_d1.txt)

Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:

  fix type and code renaming

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/38/files
  - new: https://git.openjdk.java.net/riscv-port/pull/38/files/5d745571..872b0b96

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=38&range=01
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=38&range=00-01

  Stats: 16 lines in 2 files changed: 0 ins; 3 del; 13 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/38.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/38/head:pull/38

PR: https://git.openjdk.java.net/riscv-port/pull/38

From fjiang at openjdk.java.net  Mon Dec 27 12:22:26 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Mon, 27 Dec 2021 12:22:26 GMT
Subject: [riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and
 squareToLen [v2]
In-Reply-To: <weqO_V5J5c75gV7XDUCXprxZo5aFmhznTxWfEMPZOKQ=.e9b11c78-d897-44a0-94d6-573424414d8c@github.com>
References: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
 <weqO_V5J5c75gV7XDUCXprxZo5aFmhznTxWfEMPZOKQ=.e9b11c78-d897-44a0-94d6-573424414d8c@github.com>
Message-ID: <eOUEyJTLIzel6yyADL4CZQrMwEGcts_Ft8TCloGQhqU=.27af7053-b699-4a2d-b185-1b7c8380052e@github.com>

On Mon, 27 Dec 2021 11:26:48 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   fix type and code renaming
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3249:
> 
>> 3247: 
>> 3248: /**
>> 3249:  * Multiply 128 bit by 128. Unrolled inner loop.
> 
> Should be: "Multiply 128 bit by 128 bit. Unrolled inner loop."

Fixed.

> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3381:
> 
>> 3379: 
>> 3380: /**
>> 3381:  * Code for BigInteger::multiplyToLen() instrinsic.
> 
> There is a typo here. Should be: ""Code for BigInteger::multiplyToLen() intrinsic."

Fixed.

> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3417:
> 
>> 3415:   mv(carry, zr); // carry = 0;
>> 3416: 
>> 3417:   Label L_multiply_64_or_128, L_done;
> 
> Suggestion: rename L_multiply_64_or_128 into L_multiply_64_x_64_loop

Thanks for the suggestion, renamed.

> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3424:
> 
>> 3422:   const Register jdx = tmp1;
>> 3423: 
>> 3424:   // if x and y are both 8 bytes aligend.
> 
> There is a typo here. Maybe "// Check if x and y are both 8-byte aligned."

Oops! Fixed.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/38

From fjiang at openjdk.java.net  Mon Dec 27 12:26:41 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Mon, 27 Dec 2021 12:26:41 GMT
Subject: [riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and
 squareToLen [v2]
In-Reply-To: <weqO_V5J5c75gV7XDUCXprxZo5aFmhznTxWfEMPZOKQ=.e9b11c78-d897-44a0-94d6-573424414d8c@github.com>
References: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
 <weqO_V5J5c75gV7XDUCXprxZo5aFmhznTxWfEMPZOKQ=.e9b11c78-d897-44a0-94d6-573424414d8c@github.com>
Message-ID: <Rvt37kKcwDWoBKV9PHZbcnjK4K9IoRs3nZJ5d7TupLI=.0a1c131f-341f-420f-9650-812ace791932@github.com>

On Mon, 27 Dec 2021 11:36:07 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   fix type and code renaming
>
> Changes requested by fyang (Lead).

@RealFYang  Thank you for the review. I have addressed all your comments above. :-)

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/38

From fjiang at openjdk.java.net  Mon Dec 27 12:35:21 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Mon, 27 Dec 2021 12:35:21 GMT
Subject: [riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and
 squareToLen [v3]
In-Reply-To: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
References: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
Message-ID: <F6ZE6jrReJuTjMUrFOYHrNpXxfbaUDvn_eN6gLPrT-Q=.203dc11e-935e-4322-88ad-aae436509fcd@github.com>

> BigInteger intrinsic: MultiplyToLen and SquareToLen intrinsic are missed in current vm. They should be implemented.
> The JMH tests show that the MultiplyToLen intrinsic improve the performance by up to 2x ~ 3x and the SquareToLen intrinsic improve the performance by up to 1.8x ~ 2x when the length of BigInteger changed from 1 to 5000, compared with that of C2.
> 
> Full jtreg tests on qemu and hotspot/jdk tier1 test on Unmathced are passed without new failures.
> 
> JMH tests and results on D1 and Unmatched list as follows:
> [MyBenchmark.txt](https://github.com/openjdk/riscv-port/files/7779255/MyBenchmark.txt)
> 
> [squareToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779247/squareToLen_unmatched.txt)
> [squareToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779248/squareToLen_d1.txt)
> [multiplyToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779249/multiplyToLen_unmatched.txt)
> [multiplyToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779250/multiplyToLen_d1.txt)

Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:

  fix typo

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/38/files
  - new: https://git.openjdk.java.net/riscv-port/pull/38/files/872b0b96..1d6c0cb3

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=38&range=02
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=38&range=01-02

  Stats: 4 lines in 1 file changed: 0 ins; 0 del; 4 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/38.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/38/head:pull/38

PR: https://git.openjdk.java.net/riscv-port/pull/38

From fjiang at openjdk.java.net  Mon Dec 27 12:49:13 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Mon, 27 Dec 2021 12:49:13 GMT
Subject: [riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and
 squareToLen [v4]
In-Reply-To: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
References: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
Message-ID: <mlXVfWdQ-FuF3kUynWDVjhX4ODUZNsv67p2vVsZUuBg=.98a4ed1d-b894-48f0-9769-02fa52fbef0d@github.com>

> BigInteger intrinsic: MultiplyToLen and SquareToLen intrinsic are missed in current vm. They should be implemented.
> The JMH tests show that the MultiplyToLen intrinsic improve the performance by up to 2x ~ 3x and the SquareToLen intrinsic improve the performance by up to 1.8x ~ 2x when the length of BigInteger changed from 1 to 5000, compared with that of C2.
> 
> Full jtreg tests on qemu and hotspot/jdk tier1 test on Unmathced are passed without new failures.
> 
> JMH tests and results on D1 and Unmatched list as follows:
> [MyBenchmark.txt](https://github.com/openjdk/riscv-port/files/7779255/MyBenchmark.txt)
> 
> [squareToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779247/squareToLen_unmatched.txt)
> [squareToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779248/squareToLen_d1.txt)
> [multiplyToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779249/multiplyToLen_unmatched.txt)
> [multiplyToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779250/multiplyToLen_d1.txt)

Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:

  recover deleted comment

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/38/files
  - new: https://git.openjdk.java.net/riscv-port/pull/38/files/1d6c0cb3..d5d6a5a1

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=38&range=03
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=38&range=02-03

  Stats: 1 line in 1 file changed: 0 ins; 0 del; 1 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/38.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/38/head:pull/38

PR: https://git.openjdk.java.net/riscv-port/pull/38

From fyang at openjdk.java.net  Tue Dec 28 01:35:45 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Tue, 28 Dec 2021 01:35:45 GMT
Subject: [riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and
 squareToLen [v4]
In-Reply-To: <mlXVfWdQ-FuF3kUynWDVjhX4ODUZNsv67p2vVsZUuBg=.98a4ed1d-b894-48f0-9769-02fa52fbef0d@github.com>
References: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
 <mlXVfWdQ-FuF3kUynWDVjhX4ODUZNsv67p2vVsZUuBg=.98a4ed1d-b894-48f0-9769-02fa52fbef0d@github.com>
Message-ID: <2_1_QsyJyPxmkSgdOkhy5t78Y4kaBhspu6XFGKyJCFc=.ed79277d-2224-49db-a300-ad2abf747705@github.com>

On Mon, 27 Dec 2021 12:49:13 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> BigInteger intrinsic: MultiplyToLen and SquareToLen intrinsic are missed in current vm. They should be implemented.
>> The JMH tests show that the MultiplyToLen intrinsic improve the performance by up to 2x ~ 3x and the SquareToLen intrinsic improve the performance by up to 1.8x ~ 2x when the length of BigInteger changed from 1 to 5000, compared with that of C2.
>> 
>> Full jtreg tests on qemu and hotspot/jdk tier1 test on Unmathced are passed without new failures.
>> 
>> JMH tests and results on D1 and Unmatched list as follows:
>> [MyBenchmark.txt](https://github.com/openjdk/riscv-port/files/7779255/MyBenchmark.txt)
>> 
>> [squareToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779247/squareToLen_unmatched.txt)
>> [squareToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779248/squareToLen_d1.txt)
>> [multiplyToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779249/multiplyToLen_unmatched.txt)
>> [multiplyToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779250/multiplyToLen_d1.txt)
>
> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   recover deleted comment

Changes requested by fyang (Lead).

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3424:

> 3422:   const Register jdx = tmp1;
> 3423: 
> 3424:   // Check if x and y are both 8-byte aligned.

I think the code logic for avoiding unaligned access should be under control of option AvoidUnalignedAccesses.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/38

From fjiang at openjdk.java.net  Tue Dec 28 03:01:02 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Tue, 28 Dec 2021 03:01:02 GMT
Subject: [riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and
 squareToLen [v5]
In-Reply-To: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
References: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
Message-ID: <012214Ocljw3cTRbd-Fxj1n6W-SgWPrARD0WIiTV5Xk=.3c00d4d3-0fc3-41c4-8b26-0c0762a1c688@github.com>

> BigInteger intrinsic: MultiplyToLen and SquareToLen intrinsic are missed in current vm. They should be implemented.
> The JMH tests show that the MultiplyToLen intrinsic improve the performance by up to 2x ~ 3x and the SquareToLen intrinsic improve the performance by up to 1.8x ~ 2x when the length of BigInteger changed from 1 to 5000, compared with that of C2.
> 
> Full jtreg tests on qemu and hotspot/jdk tier1 test on Unmathced are passed without new failures.
> 
> JMH tests and results on D1 and Unmatched list as follows:
> [MyBenchmark.txt](https://github.com/openjdk/riscv-port/files/7779255/MyBenchmark.txt)
> 
> [squareToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779247/squareToLen_unmatched.txt)
> [squareToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779248/squareToLen_d1.txt)
> [multiplyToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779249/multiplyToLen_unmatched.txt)
> [multiplyToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779250/multiplyToLen_d1.txt)

Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:

  and avoid unaligned accesses option

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/38/files
  - new: https://git.openjdk.java.net/riscv-port/pull/38/files/d5d6a5a1..ae5180aa

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=38&range=04
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=38&range=03-04

  Stats: 66 lines in 1 file changed: 16 ins; 14 del; 36 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/38.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/38/head:pull/38

PR: https://git.openjdk.java.net/riscv-port/pull/38

From duke at openjdk.java.net  Tue Dec 28 03:24:42 2021
From: duke at openjdk.java.net (guotaiping1)
Date: Tue, 28 Dec 2021 03:24:42 GMT
Subject: [riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and
 squareToLen [v4]
In-Reply-To: <2_1_QsyJyPxmkSgdOkhy5t78Y4kaBhspu6XFGKyJCFc=.ed79277d-2224-49db-a300-ad2abf747705@github.com>
References: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
 <mlXVfWdQ-FuF3kUynWDVjhX4ODUZNsv67p2vVsZUuBg=.98a4ed1d-b894-48f0-9769-02fa52fbef0d@github.com>
 <2_1_QsyJyPxmkSgdOkhy5t78Y4kaBhspu6XFGKyJCFc=.ed79277d-2224-49db-a300-ad2abf747705@github.com>
Message-ID: <BP6Xq7hlo7tSwuhhwaejBDZIG4nQGTWyj_p0qmIp6vk=.8a76c763-54a6-411d-ae39-ac3b3e81a511@github.com>

On Tue, 28 Dec 2021 01:32:08 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   recover deleted comment
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3424:
> 
>> 3422:   const Register jdx = tmp1;
>> 3423: 
>> 3424:   // Check if x and y are both 8-byte aligned.
> 
> I think the code logic for avoiding unaligned access should be under control of option AvoidUnalignedAccesses.

The cod logic for avoiding unaligned access has been placed under the control of the AvoidUnalignedAccesses option, and the test cases related to BIgInteger are all passed when `-XX:-AvoidUnalignedAccesses` and `-XX:+AvoidUnalignedAccesses`. Thanks for your review!

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/38

From fjiang at openjdk.java.net  Wed Dec 29 02:18:16 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Wed, 29 Dec 2021 02:18:16 GMT
Subject: [riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and
 squareToLen [v6]
In-Reply-To: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
References: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
Message-ID: <HhKnIre4w5aVMVjezBdEHLY_sz3l2bU7m53jEzvWEVM=.4a9c1acf-8f20-41dd-91cf-67b5568eeef5@github.com>

> BigInteger intrinsic: MultiplyToLen and SquareToLen intrinsic are missed in current vm. They should be implemented.
> The JMH tests show that the MultiplyToLen intrinsic improve the performance by up to 2x ~ 3x and the SquareToLen intrinsic improve the performance by up to 1.8x ~ 2x when the length of BigInteger changed from 1 to 5000, compared with that of C2.
> 
> Full jtreg tests on qemu and hotspot/jdk tier1 test on Unmathced are passed without new failures.
> 
> JMH tests and results on D1 and Unmatched list as follows:
> [MyBenchmark.txt](https://github.com/openjdk/riscv-port/files/7779255/MyBenchmark.txt)
> 
> [squareToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779247/squareToLen_unmatched.txt)
> [squareToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779248/squareToLen_d1.txt)
> [multiplyToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779249/multiplyToLen_unmatched.txt)
> [multiplyToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779250/multiplyToLen_d1.txt)

Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:

  use 32-bit instructions to deal with length and index operations

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/38/files
  - new: https://git.openjdk.java.net/riscv-port/pull/38/files/ae5180aa..aca73fbe

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=38&range=05
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=38&range=04-05

  Stats: 31 lines in 1 file changed: 1 ins; 0 del; 30 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/38.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/38/head:pull/38

PR: https://git.openjdk.java.net/riscv-port/pull/38

From fyang at openjdk.java.net  Wed Dec 29 03:11:33 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Wed, 29 Dec 2021 03:11:33 GMT
Subject: [riscv-port] RFR: 8279292: riscv: Intrinsify multiplyToLen and
 squareToLen [v6]
In-Reply-To: <HhKnIre4w5aVMVjezBdEHLY_sz3l2bU7m53jEzvWEVM=.4a9c1acf-8f20-41dd-91cf-67b5568eeef5@github.com>
References: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
 <HhKnIre4w5aVMVjezBdEHLY_sz3l2bU7m53jEzvWEVM=.4a9c1acf-8f20-41dd-91cf-67b5568eeef5@github.com>
Message-ID: <9k_rxZoZ7v-YsTYpsmRHYKtAgWK9wlprr5j-ndF8kB8=.cbc93d9b-ceae-4c46-909c-5540e5463170@github.com>

On Wed, 29 Dec 2021 02:18:16 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> BigInteger intrinsic: MultiplyToLen and SquareToLen intrinsic are missed in current vm. They should be implemented.
>> The JMH tests show that the MultiplyToLen intrinsic improve the performance by up to 2x ~ 3x and the SquareToLen intrinsic improve the performance by up to 1.8x ~ 2x when the length of BigInteger changed from 1 to 5000, compared with that of C2.
>> 
>> Full jtreg tests on qemu and hotspot/jdk tier1 test on Unmathced are passed without new failures.
>> 
>> JMH tests and results on D1 and Unmatched list as follows:
>> [MyBenchmark.txt](https://github.com/openjdk/riscv-port/files/7779255/MyBenchmark.txt)
>> 
>> [squareToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779247/squareToLen_unmatched.txt)
>> [squareToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779248/squareToLen_d1.txt)
>> [multiplyToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779249/multiplyToLen_unmatched.txt)
>> [multiplyToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779250/multiplyToLen_d1.txt)
>
> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   use 32-bit instructions to deal with length and index operations

Looks good.

-------------

Marked as reviewed by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/38

From fyang at openjdk.java.net  Wed Dec 29 03:13:44 2021
From: fyang at openjdk.java.net (Fei Yang)
Date: Wed, 29 Dec 2021 03:13:44 GMT
Subject: git: openjdk/riscv-port: riscv-port: 8279292: riscv: Intrinsify
 multiplyToLen and squareToLen
Message-ID: <7a69d0d2-db3c-489a-9124-1d4ad41e8e1f@openjdk.org>

Changeset: b396cdda
Author:    Feilong Jiang <fjiang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
Date:      2021-12-29 03:13:11 +0000
URL:       https://git.openjdk.java.net/riscv-port/commit/b396cdda88b703918fe89d80261b08bb22c64e76

8279292: riscv: Intrinsify multiplyToLen and squareToLen

Co-authored-by: Taiping Guo <guotaiping1 at huawei.com>
Reviewed-by: fyang

! src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
! src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
! src/hotspot/cpu/riscv/stubGenerator_riscv.cpp
! src/hotspot/cpu/riscv/vm_version_riscv.cpp


From fjiang at openjdk.java.net  Wed Dec 29 03:17:36 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Wed, 29 Dec 2021 03:17:36 GMT
Subject: [riscv-port] Integrated: 8279292: riscv: Intrinsify multiplyToLen and
 squareToLen
In-Reply-To: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
References: <gydE6oHm9GTOlFx0-1Ipv1gw2_IxFp4DJr60AEqfG5g=.db11faed-7749-456d-89a9-825eaa53f0da@github.com>
Message-ID: <n3GizvQFJGxGTdq-dEDkpft9_XWoRGIZQV9crkqKcKE=.1330dc7d-63d7-42cc-988f-e78062e4cca2@github.com>

On Mon, 27 Dec 2021 08:25:22 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> BigInteger intrinsic: MultiplyToLen and SquareToLen intrinsic are missed in current vm. They should be implemented.
> The JMH tests show that the MultiplyToLen intrinsic improve the performance by up to 2x ~ 3x and the SquareToLen intrinsic improve the performance by up to 1.8x ~ 2x when the length of BigInteger changed from 1 to 5000, compared with that of C2.
> 
> Full jtreg tests on qemu and hotspot/jdk tier1 test on Unmathced are passed without new failures.
> 
> JMH tests and results on D1 and Unmatched list as follows:
> [MyBenchmark.txt](https://github.com/openjdk/riscv-port/files/7779255/MyBenchmark.txt)
> 
> [squareToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779247/squareToLen_unmatched.txt)
> [squareToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779248/squareToLen_d1.txt)
> [multiplyToLen_unmatched.txt](https://github.com/openjdk/riscv-port/files/7779249/multiplyToLen_unmatched.txt)
> [multiplyToLen_d1.txt](https://github.com/openjdk/riscv-port/files/7779250/multiplyToLen_d1.txt)

This pull request has now been integrated.

Changeset: b396cdda
Author:    Feilong Jiang <fjiang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/b396cdda88b703918fe89d80261b08bb22c64e76
Stats:     595 lines in 4 files changed: 589 ins; 0 del; 6 mod

8279292: riscv: Intrinsify multiplyToLen and squareToLen

Co-authored-by: Taiping Guo <guotaiping1 at huawei.com>
Reviewed-by: fyang

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/38

From fjiang at openjdk.java.net  Fri Dec 31 03:57:49 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Fri, 31 Dec 2021 03:57:49 GMT
Subject: [riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation
 instructions
Message-ID: <ONbvJgG0Cge0DTomGGDL5Bs-2XAU3tzsbVGS2KvrV1A=.99e30de1-1987-4d29-aec2-8f68caf8ad44@github.com>

This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw.

This PR also add zext/bext C2 instructions that were missed in JDK-8279213

-------------

Commit messages:
 - 8279344: riscv: RVB: Add bitwise rotation instructions

Changes: https://git.openjdk.java.net/riscv-port/pull/39/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8279344
  Stats: 417 lines in 6 files changed: 396 ins; 1 del; 20 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39

PR: https://git.openjdk.java.net/riscv-port/pull/39

From fjiang at openjdk.java.net  Fri Dec 31 05:09:23 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Fri, 31 Dec 2021 05:09:23 GMT
Subject: [riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation
 instructions [v2]
In-Reply-To: <ONbvJgG0Cge0DTomGGDL5Bs-2XAU3tzsbVGS2KvrV1A=.99e30de1-1987-4d29-aec2-8f68caf8ad44@github.com>
References: <ONbvJgG0Cge0DTomGGDL5Bs-2XAU3tzsbVGS2KvrV1A=.99e30de1-1987-4d29-aec2-8f68caf8ad44@github.com>
Message-ID: <bKsWS7zMWQSUeAcheNinSRHGQV9Tq6GVPr4b8XjJdtE=.6d57cad6-ecda-4d95-a58b-2555a9a4798f@github.com>

> This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw.
> 
> This PR also add zext/bext C2 instructions that were missed in JDK-8279213

Feilong Jiang has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision:

  8279344: riscv: RVB: Add bitwise rotation instructions

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/39/files
  - new: https://git.openjdk.java.net/riscv-port/pull/39/files/7c081e52..565fd2e2

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=01
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=00-01

  Stats: 5 lines in 1 file changed: 1 ins; 0 del; 4 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39

PR: https://git.openjdk.java.net/riscv-port/pull/39

From fjiang at openjdk.java.net  Fri Dec 31 08:57:04 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Fri, 31 Dec 2021 08:57:04 GMT
Subject: [riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation
 instructions [v3]
In-Reply-To: <ONbvJgG0Cge0DTomGGDL5Bs-2XAU3tzsbVGS2KvrV1A=.99e30de1-1987-4d29-aec2-8f68caf8ad44@github.com>
References: <ONbvJgG0Cge0DTomGGDL5Bs-2XAU3tzsbVGS2KvrV1A=.99e30de1-1987-4d29-aec2-8f68caf8ad44@github.com>
Message-ID: <Fsy7xJKlSfiKFxTHUl2oDdhEwHlJjvSJIyx1XAlPg7A=.85a7bdf1-f99e-4487-bb81-1b02cfe71d74@github.com>

> This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw.
> 
> This PR also add zext/bext C2 instructions that were missed in JDK-8279213

Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:

  remove unused instruction in riscv_b.ad

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/39/files
  - new: https://git.openjdk.java.net/riscv-port/pull/39/files/565fd2e2..d9f91328

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=02
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=01-02

  Stats: 118 lines in 1 file changed: 0 ins; 118 del; 0 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39

PR: https://git.openjdk.java.net/riscv-port/pull/39

From fjiang at openjdk.java.net  Fri Dec 31 09:15:14 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Fri, 31 Dec 2021 09:15:14 GMT
Subject: [riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation
 instructions [v4]
In-Reply-To: <ONbvJgG0Cge0DTomGGDL5Bs-2XAU3tzsbVGS2KvrV1A=.99e30de1-1987-4d29-aec2-8f68caf8ad44@github.com>
References: <ONbvJgG0Cge0DTomGGDL5Bs-2XAU3tzsbVGS2KvrV1A=.99e30de1-1987-4d29-aec2-8f68caf8ad44@github.com>
Message-ID: <e_BSEuZEhKHufFj6hm_x5P40heBVnDn0gN8exMUUVio=.05a9d3d0-faac-44ac-917d-7b832e20d5fd@github.com>

> This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw.
> 
> This PR also add zext/bext C2 instructions that were missed in JDK-8279213

Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:

  remove unused imm definition

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/39/files
  - new: https://git.openjdk.java.net/riscv-port/pull/39/files/d9f91328..2fd614c1

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=03
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=02-03

  Stats: 47 lines in 1 file changed: 0 ins; 47 del; 0 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39

PR: https://git.openjdk.java.net/riscv-port/pull/39

From yzhu at openjdk.java.net  Fri Dec 31 09:18:52 2021
From: yzhu at openjdk.java.net (Yanhong Zhu)
Date: Fri, 31 Dec 2021 09:18:52 GMT
Subject: [riscv-port] RFR: 8279346: riscv: Unnecessary sign extension in
 BigInteger intrinsics
Message-ID: <6rczN2yxo3a_Jp1b42HKiNqDw0ashboHLDqqoEH7tqM=.648ec3d1-66f6-4925-9162-5461fd58f022@github.com>

Reference: https://github.com/riscv-non-isa/riscv-elf-psabi-doc

" Scalars that are at most XLEN bits wide are passed in a single argument register, or on the stack by value if none is available.
When passed in registers or on the stack, integer scalars narrower than XLEN bits are widened according to the sign of their type up to 32 bits, then sign-extended to XLEN bits.
When passed in registers or on the stack, floating-point types narrower than XLEN bits are widened to XLEN bits, with the upper bits undefined."

So there is no need to do sign extension for signed integer input parameters.

-------------

Commit messages:
 - 8279346: riscv: Unnecessary sign extension in BigInteger intrinsics

Changes: https://git.openjdk.java.net/riscv-port/pull/40/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=40&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8279346
  Stats: 41 lines in 4 files changed: 4 ins; 8 del; 29 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/40.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/40/head:pull/40

PR: https://git.openjdk.java.net/riscv-port/pull/40

From fjiang at openjdk.java.net  Fri Dec 31 10:07:06 2021
From: fjiang at openjdk.java.net (Feilong Jiang)
Date: Fri, 31 Dec 2021 10:07:06 GMT
Subject: [riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation
 instructions [v5]
In-Reply-To: <ONbvJgG0Cge0DTomGGDL5Bs-2XAU3tzsbVGS2KvrV1A=.99e30de1-1987-4d29-aec2-8f68caf8ad44@github.com>
References: <ONbvJgG0Cge0DTomGGDL5Bs-2XAU3tzsbVGS2KvrV1A=.99e30de1-1987-4d29-aec2-8f68caf8ad44@github.com>
Message-ID: <WgoVybAxRLbNLf6HEl747gKZubBGpqQJYCQPEapHVOQ=.90460ee4-87f6-4cac-8e01-8cb1da47a7b4@github.com>

> This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw.
> 
> This PR also add zext/bext C2 instructions that were missed in JDK-8279213

Feilong Jiang has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision:

  remove unused imm definition

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/39/files
  - new: https://git.openjdk.java.net/riscv-port/pull/39/files/2fd614c1..428e2151

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=04
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=03-04

  Stats: 19 lines in 1 file changed: 19 ins; 0 del; 0 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39

PR: https://git.openjdk.java.net/riscv-port/pull/39