[riscv-port] RFR: 8278034: riscv: Fix callee-saved float register definitions: should be SOE

[Xiaolin Zheng]

On Wed, 1 Dec 2021 02:43:12 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> There are unnecessary float register spills before leaf calls and it seems that callee-saved float registers' definitions should be SOE so the register allocator may firstly use these SOE registers as allocation candidates to prevent spills before leaf calls. I have looked through F8-F9, F18-F27 usages and found they are not used in any stub so it could be safe. Tested all cases. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/13)
> 
> This fix is nearly the same as [JDK-8253048](https://bugs.openjdk.java.net/browse/JDK-8253048)'s [PR](https://github.com/openjdk/jdk/pull/129) on the aarch64 platform and receives an identical result.

Thank you for reviewing this -

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PR: https://git.openjdk.java.net/riscv-port/pull/20