[riscv-port] RFR: 8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate

[Xiaolin Zheng]

On Mon, 29 Nov 2021 15:06:51 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> This bug can be reproduced by `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1 -version` on the unmatched board where this command will hang. The reason is that the implementation of load reserved/store conditional loop in BarrierSetAssembler::eden_allocate breaks the RISC-V Atomic extension spec:
> 
> For the
> sequence to be guaranteed to eventually succeed, the dynamic code executed between the LR and
> SC instructions can only contain other instructions from the base \I" subset, excluding loads, stores,
> backward jumps or taken backward branches, FENCE, FENCE.I, and SYSTEM instructions.
> 
> It may cause an unspecified behaviour depends on specific hardware implementations.

Thank you for fixing this. Qemu and C910 cannot reveal this issue so I didn't notice it.  :-(   
I just tested this `-XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1` on both a D1 and an unleashed board, and this issue was reproduced without this patch.

No need to reply -- it is just a comment.

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PR: https://git.openjdk.java.net/riscv-port/pull/17