[riscv-port] RFR: 8278033: riscv: Fix MacroAssembler::atomic_incw: store condition instruction has wrong operand order

[Aleksey Shipilev]

On Wed, 1 Dec 2021 10:37:15 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Thank you for your insight -- though I have no access to the history of this part of code, IMO it may be derived from [the AArch64 counterpart](https://github.com/openjdk/riscv-port/blob/master/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp#L1551-L1567). Seems it only undertakes a simple counting behavior for BiasedLocking before JDK18, like [this code at jdk17-ga](https://github.com/openjdk/jdk/blob/dfacda488bfbe2e11e8d607a6d08527710286982/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp#L487). Currently this function has no usage in both sides of back-ends. I guess this counting behavior may not be so precise? I'm not so good at it and hope I could learn something.

This is not about counting behavior, but rather about the transitive memory ordering from the counters. But I see that AArch64 ` MacroAssembler::atomic_incw` indeed uses `ldxrw`/`stxrw`, which carry no implicit memory ordering. So, this is fine for a single counter in RISC-V too.

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PR: https://git.openjdk.java.net/riscv-port/pull/19