[riscv-port] Withdrawn: 8277968: riscv: Detect vector extension with vcsr

[kuaiwei]

On Tue, 30 Nov 2021 07:22:04 GMT, kuaiwei <duke at openjdk.java.net> wrote:

> UseRVV could cause crash on D1 board(RISCV-C906).
> 
> It seems that though the D1 board is equipped with RVV-0.7.1[1] . In our test, VLENB CSR can return value of 16 on D1 board. So JDK will assume it can support RVV extension and crash in vector instructions when  UseRVV is enabled.  
> 
> RVV-0.9 and above[2] introduce a new VCSR CSR register, it will raise SIGILL on D1 board. So we can check it to detect vext support.
> 
> 
> [1] https://github.com/riscv/riscv-v-spec/blob/0a24d0f61b5cd3f1f9265e8c40ab211daa865ede/v-spec.adoc#vector-extension-programmers-model
> [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-extension-programmers-model

This pull request has been closed without being integrated.

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PR: https://git.openjdk.java.net/riscv-port/pull/18