[riscv-port] RFR: 8278192: riscv: remove unnecessary instruct of DecodeNKlass in C2

[Yadong Wang]

On Fri, 3 Dec 2021 10:45:08 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> There are two instructs for DecodeNKlass in C2, and the difference is only that which temporary register operand is used by them, xheapbase, t0 or t1. It's too complicated and the effect is almost invisible. So we just simplify the pattern by using a temporary register from the register allocation.
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 2202:
> 
>> 2200:   Label retry_load, nope;
>> 2201:   bind(retry_load);
>> 2202:   // flush and load exclusive from the memory location
> 
> Could you please also fix the comments in MacroAssembler::atomic_incw? Thanks

atomic_incw has not been called anywhere, so I'll remove it in the next commit.

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PR: https://git.openjdk.java.net/riscv-port/pull/22