[riscv-port] RFR: 8278743: riscv: Remove the x4 register saving logic in Java frames
Xiaolin Zheng
xlinzheng at openjdk.java.net
Tue Dec 14 04:32:56 UTC 2021
Hi team,
x4 is the thread pointer register and would be modified by the kernel. With this respect, we shall not modify or change its value. In the riscv-port repo, we have no other modifications for the x4 register so I would recommend removing the x4 saving logic in java frames. I have verified this change along with other patches under jdk/hotspot full tiers on different boards and qemu.
BTW, due to the logic that can automatically adjust the sp to 16-byte aligned[1], it is safe to change the `sp_after_call_off` to an odd number.
[1] https://github.com/openjdk/riscv-port/blob/riscv-port/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp#L277
Thanks,
Xiaolin
-------------
Commit messages:
- Remove x4 in java frames
Changes: https://git.openjdk.java.net/riscv-port/pull/29/files
Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=29&range=00
Issue: https://bugs.openjdk.java.net/browse/JDK-8278743
Stats: 32 lines in 2 files changed: 0 ins; 6 del; 26 mod
Patch: https://git.openjdk.java.net/riscv-port/pull/29.diff
Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/29/head:pull/29
PR: https://git.openjdk.java.net/riscv-port/pull/29
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