[riscv-port] Integrated: 8278743: riscv: Remove the x4 register saving logic in Java frames

[Xiaolin Zheng]

On Tue, 14 Dec 2021 04:27:20 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
> 
> x4 is the thread pointer register and would be modified by the kernel. With this respect, we shall not modify or change its value. In the riscv-port repo, we have no other modifications for the x4 register so I would recommend removing the x4 saving logic in java frames. I have verified this change along with other patches under jdk/hotspot full tiers on different boards and qemu.
> 
> BTW, due to the logic that can automatically adjust the sp to 16-byte aligned[1], it is safe to change the `sp_after_call_off` to an odd number.
> 
> [1] https://github.com/openjdk/riscv-port/blob/riscv-port/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp#L277
> 
> Thanks,
> Xiaolin

This pull request has now been integrated.

Changeset: 3a9a1eb9
Author:    Xiaolin Zheng <xlinzheng at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/3a9a1eb94bf737c4355d473b2a86b03c46fbaa99
Stats:     32 lines in 2 files changed: 0 ins; 6 del; 26 mod

8278743: riscv: Remove the x4 register saving logic in Java frames

Reviewed-by: fyang

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PR: https://git.openjdk.java.net/riscv-port/pull/29