[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v2]

[Xiaolin Zheng]

On Wed, 15 Dec 2021 09:01:46 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> Thanks for the nice reminder -- changed.
>
> Need some testing work for the new change -- I will ping this thread after tests are done.

`test/jtreg/hotspot/compiler` on Qemu reveals no other errors.

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PR: https://git.openjdk.java.net/riscv-port/pull/31