CFV: New RISC-V Port Committer: Yanhong Zhu

[Yangfei (Felix)]

Vote: yes

> -----Original Message-----
> From: Yangfei (Felix)
> Sent: Monday, December 20, 2021 5:12 PM
> To: 'riscv-port-dev at openjdk.java.net' <riscv-port-dev at openjdk.java.net>
> Subject: CFV: New RISC-V Port Committer: Yanhong Zhu
> 
> I hereby nominate Yanhong Zhu (yzhu) to RISC-V Port Committer.
> 
> Yanhong Zhu has been engaged in the development of the OpenJDK riscv-
> port since 2020.
> She has contributed 8 sponsored patches to JDK and RISC-V Port project.
> 
> Votes are due by 9:00 UTC on Monday 3, January 2022.
> 
> Only current RISC-V Port Committers [1] are eligible to vote on this
> nomination.
> Votes must be cast in the open by replying to this mailing list.
> 
> For Lazy Consensus voting instructions, see [2].
> 
> Thanks,
> Felix
> 
> [1] https://openjdk.java.net/census
> [2] https://openjdk.java.net/projects/#committer-vote
> 
> =========
> 
> 8255287: aarch64: fix SVE patterns for vector shift count
> 8276792: RISC-V Port: Initial support for RV64GV
> 8277167: riscv: Remove unnecessary register declaration for lr
> 8277036: riscv: Get CPU features from the auxiliary vector on Linux
> 8277440: riscv: Move UseVExt from product to experimental
> 8276832: riscv: typo in LIR_Assembler::check_no_conflict
> 8278547: riscv: Refactor moving assembler functions for vector instructions
> into separate file
> 8278895: riscv: Rename Riscv64 to RISCV64