[riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd

[Feilong Jiang]

BigInteger intrinsic: mulAdd intrinsic is missed in current vm. It should be implemented.
The JMH test of mulAdd intrinsic on the matched board shows that the performance can be improved by 0.69%~21.91% when the length of BigInteger changed from 1 to 5000, compared with that of C2.
| length | intrinsic(ops/ms) | no intrinsic(ops/ms) | intrinsic / no intrinsic |
| ------ | ------ | ------ | ------ | 
| 1 | 1643.111 | 1623.814 | 1.18% |
| 2 | 1597.927 | 1585.216 | 0.80% |
| 3 | 1542.249 | 1502.455 | 2.65% |
| 5 | 1533.371 | 1522.837 | 0.69% |
| 10 | 1377.683 | 1361.718 | 1.17% |
| 50 | 925.826 | 844.276 | 9.62% |
| 100 | 638.767 | 576.276 | 10.84% |
| 1000 | 99.870 | 84.796 | 17.78% |
| 2000 | 51.511 | 43.624 | 18.08% |
| 5000 | 18.017 | 14.779 | 21.91% |

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Commit messages:
 - 8278644: riscv: Intrinsify mulAdd

Changes: https://git.openjdk.java.net/riscv-port/pull/36/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=36&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278644
  Stats: 106 lines in 4 files changed: 106 ins; 0 del; 0 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/36.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/36/head:pull/36

PR: https://git.openjdk.java.net/riscv-port/pull/36